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Sreehari Veeramachaneni
Sreehari Veeramachaneni
Unknown affiliation
Verified email at research.iiit.ac.in
Title
Cited by
Cited by
Year
Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressors
S Veeramachaneni, KM Krishna, L Avinash, SR Puppala, MB Srinivas
20th International Conference on VLSI Design held jointly with 6th …, 2007
1532007
New improved 1-bit adder cells
SMBS Veeramachaneni
Canadian Conference on Electrical and Computer Engineering, 735-738, 2008
66*2008
Schmitt trigger as an alternative to buffer insertion for delay and power reduction in VLSI interconnects
S Saini, S Veeramachaneni, AM Kumar, MB Srinivas
TENCON 2009-2009 IEEE Region 10 Conference, 1-5, 2009
372009
2: 1 Multiplexer based design for ternary logic circuits
C Vudadha, S Katragadda, PS Phaneendra
2013 IEEE Asia Pacific Conference on Postgraduate Research in …, 2013
282013
Design of a low power, variable-resolution flash ADC
S Veeramachanen, AM Kumar, V Tummala, MB Srinivas
2009 22nd International Conference on VLSI Design, 117-122, 2009
282009
Novel architectures for efficient (m, n) parallel counters
S Veeramachaneni, A Lingamneni, MK Krishna, MB Srinivas
Proceedings of the 17th ACM Great Lakes symposium on VLSI, 188-191, 2007
272007
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects
S Saini, AM Kumar, S Veeramachaneni, MB Srinivas
Journal of Low Power Electronics 6 (3), 429-435, 2010
252010
Novel, high-speed 16-digit BCD adders conforming to IEEE 754r format
S Veeramachaneni, MK Krishna, L Avinash, S Reddy, MB Srinivas
IEEE Computer Society Annual Symposium on VLSI (ISVLSI'07), 343-350, 2007
242007
CNFET based ternary magnitude comparator
C Vudadha, PP Sai, V Sreehari, MB Srinivas
2012 International Symposium on Communications and Information Technologies …, 2012
222012
Novel high-speed architecture for 32-bit binary coded decimal (bcd) multiplier
S Veeramachaneni, MB Srinivas
2008 International Symposium on Communications and Information Technologies …, 2008
212008
Design of prefix-based optimal reversible comparator
C Vudadha, PS Phaneendra, V Sreehari, SE Ahmed, NM Muthukrishnan, ...
2012 IEEE Computer Society Annual Symposium on VLSI, 201-206, 2012
202012
Low-power self reconfigurable multiplexer based decoder for adaptive resolution flash adcs
C Vudadha, G Makkena, MVS Nayudu, PS Phaneendra, SE Ahmed, ...
2012 25th International Conference on VLSI Design, 280-285, 2012
202012
Efficient design of 32-bit comparator using carry look-ahead logic
S Veeramachaneni, MK Krishna, L Avinash, RP Sreekanth, MB Srinivas
2007 IEEE Northeast Workshop on Circuits and Systems, 867-870, 2007
172007
A novel high-speed binary and gray incrementer/decrementer for an address generation unit
S Veeramachaneni, L Avinash, MB Srinivas
2007 International Conference on Industrial and Information Systems, 427-430, 2007
162007
A high performance unified BCD and binary adder/subtractor
A Singh, A Gupta, S Veeramachaneni, MB Srinivas
2009 IEEE Computer Society Annual Symposium on VLSI, 211-216, 2009
132009
A novel, low-power array multiplier architecture
R Bajaj, S Chhabra, S Veeramachaneni, MB Srinivas
2009 9th International Symposium on Communications and Information …, 2009
122009
A modified twin precision multiplier with 2D bypassing technique
SE Ahmed, S Abraham, S Veeramanchaneni, MB Srinivas
2012 International Symposium on Electronic System Design (ISED), 102-106, 2012
112012
Novel architectures for high-speed and low-power 3-2, 4-2 and 5-2 compressor
V Sreehari, M Kirthi, A Lingamneni, R Sreekanth, MB Srinivas
IEEE 20th International Conference on VLSI Design, 324-329, 2007
112007
An optimized design of reversible quantum comparator
PS Phaneendra, C Vudadha, V Sreehari, MB Srinivas
2014 27th International Conference on VLSI Design and 2014 13th …, 2014
102014
Efficient Modulo (2k±1) Binary to Residue Converters
S Veeramachaneni, L Avinash, MR Reddy, MB Srinivas
2006 6th International Workshop on System on Chip for Real Time Applications …, 2006
92006
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