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David Chinnery
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Cited by
Year
Closing the Gap Between ASIC and Custom: Tools and Techniques for High-Performance ASIC Design
D Chinnery, K Keutzer
Springer Science & Business Media, 2002
3042002
Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
D Nguyen, A Davare, M Orshansky, D Chinnery, B Thompson, K Keutzer
International Symposium on Low Power Electronics and Design, 158-163, 2003
2022003
Closing the gap between ASIC and custom: An ASIC perspective
DG Chinnery, K Keutzer
Design Automation Conference 37, 637-642, 2000
1142000
ISPD 2015 benchmarks with fence regions and routing blockages for detailed-routing-driven placement
IS Bustany, D Chinnery, JR Shinnerl, V Yutsis
International Symposium on Physical Design, 157-164, 2015
1062015
Linear programming for sizing, Vth and Vdd assignment
DG Chinnery, K Keutzer
International Symposium on Low Power Electronics and Design, 149-154, 2005
922005
Closing the Power Gap between ASIC and Custom - Tools and Techniques for Low Power Design
D Chinnery, K Keutzer
Springer Science & Business Media, 2007
752007
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement
V Yutsis, IS Bustany, D Chinnery, JR Shinnerl, WH Liu
International Symposium on Physical Design, 161-168, 2014
672014
A functional validation technique: biased-random simulation guided by observability-based coverage
S Tasiran, F Fallah, DG Chinnery, SJ Weber, K Keutzer
International Conference on Computer Design, 82-88, 2001
542001
Closing the Power Gap Between ASIC and Custom: an ASIC Perspective
DG Chinnery, K Keutzer
Design Automation Conference, 275-280, 2005
532005
Low power multiplication algorithm for switching activity reduction through operand decomposition
M Ito, D Chinnery, K Keutzer
International Conference on Computer Design, 21-26, 2003
422003
Achieving 550 MHz in an ASIC methodology
DG Chinnery, B Nikolic, K Keutzer
Design Automation Conference, 420-425, 2001
382001
Automatic replacement of flip-flops by latches in ASICs
D Chinnery, K Keutzer, J Sanghavi, E Killian, K Sheth
Closing the Gap Between ASIC and Custom: Tools and Techniques for High …, 2002
192002
Fast Lagrangian Relaxation based gate sizing using multi-threading
A Sharma, D Chinnery, S Bhardwaj, C Chu
International Conference on Computer-Aided Design, 426-433, 2015
152015
Low Power Design Automation
DG Chinnery
University of California, Berkeley, 2006
142006
Reducing the timing overhead
D Chinnery, K Keutzer
Closing the Gap Between ASIC and Custom: Tools and Techniques for High …, 2002
142002
Overview of the Factors Affecting the Power Consumption
D Chinnery, K Keutzer
Closing the Power Gap between ASIC & Custom: Tools and Techniques for Low …, 2007
112007
Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations
A Sharma, D Chinnery, T Reimann, S Bhardwaj, C Chu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020
92020
Rapid gate sizing with fewer iterations of lagrangian relaxation
A Sharma, D Chinnery, S Dhamdhere, C Chu
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 337-343, 2017
92017
High performance and low power design techniques for ASIC and custom in nanometer technologies
D Chinnery
International Symposium on Physical Design, 25-32, 2013
92013
Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach
A Sharma, D Chinnery, C Chu
International Symposium on Physical Design, 129-137, 2019
72019
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