| SleepTalker: A ULV 802.15. 4a IR-UWB transmitter SoC in 28-nm FDSOI achieving 14 pJ/b at 27 Mb/s with channel selection based on adaptive FBB and digitally programmable pulse … G de Streel, F Stas, T Gurne, F Durant, C Frenkel, A Cathelin, D Bol IEEE Journal of Solid-State Circuits 52 (4), 1163-1177, 2017 | 68 | 2017 |
| Bellevue: A 50MHz variable-width SIMD 32bit microcontroller at 0.37 V for processing-intensive wireless sensor nodes F Botman, J De Vos, S Bernard, F Stas, JD Legat, D Bol 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1207-1210, 2014 | 41 | 2014 |
| 19.6 A 40-to-80MHz Sub-4μw/mhz ULV cortex-M0 MCU SoC in 28nm FDSOI with dual-loop adaptive back-bias generator for 20μs wake-up from deep fully retentive sleep mode D Bol, M Schramme, L Moreau, T Haine, P Xu, C Frenkel, R Dekimpe, ... 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 322-324, 2019 | 34 | 2019 |
| A 0.4-V 0.66-fJ/cycle retentive true-single-phase-clock 18T flip-flop in 28-nm fully-depleted SOI CMOS F Stas, D Bol IEEE Transactions on Circuits and Systems I: Regular Papers 65 (3), 935-945, 2017 | 34 | 2017 |
| An 80-MHz 0.4 V ULV SRAM macro in 28nm FDSOI achieving 28-fJ/bit access energy with a ULP bitcell and on-chip adaptive back bias generation T Haine, QK Nguyen, F Stas, L Moreau, D Flandre, D Bol ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, 312-315, 2017 | 14 | 2017 |
| A 0.4 V 0.08 fJ/cycle retentive true-single-phase-clock 18T flip-flop in 28nm FDSOI CMOS F Stas, D Bol 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | 9 | 2017 |
| Sizing and layout integrated optimizer for 28nm analog circuits using digital PnR tools F Stas, G de Streel, D Bol 2016 14th IEEE International New Circuits and Systems Conference (NEWCAS), 1-4, 2016 | 9 | 2016 |
| Improving noise and linearity of CMOS wideband inductorless balun LNAs for 10-GHz software-defined radios in 28nm FDSOI C Gimeno, F Stas, G de Streel, D Bol, D Flandre 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2017 | 5 | 2017 |
| Automated layout-integrated sizing of a 2.45 GHz differential-drive rectifier in 28 nm FDSOI CMOS PA Haddad, F Stas, JP Raskin, D Bol, D Flandre 2017 IEEE Wireless Power Transfer Conference (WPTC), 1-4, 2017 | 5 | 2017 |
| Investigation of the routing algorithm in a De Bruijn-based NoC for low-power applications F Stas, AK Lusala, JD Legat, D Bol 2013 IEEE Faible Tension Faible Consommation, 1-4, 2013 | 4 | 2013 |
| SleepTalker: A 28nm FDSOI ULV 802.15. 4a IR-UWB transmitter SoC achieving 14pJ/bit at 27Mb/s with adaptive-FBB-based channel selection and programmable pulse shape G de Streel, F Stas, T Gurné, F Durant, C Frenkel, D Bol 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1-2, 2016 | 3 | 2016 |
| Optimization of the area/robustness/speed trade-off in a 28 nm FDSOI latch based on ULP diodes T Haine, F Stas, D Bol 2014 IEEE Faible Tension Faible Consommation, 1-4, 2014 | 3 | 2014 |
| CAMEL: An ultra-low-power VGA CMOS imager based on a time-based DPS array T Haine, F Stas, G de Streel, C Gimeno, D Flandre, D Bol Proceedings of the 10th International Conference on Distributed Smart Camera …, 2016 | 2 | 2016 |
| Method and device for charging a storage device with energy from an energy harvester J De Vos, G Gosset, C Hocquet, F Stas US Patent 11,770,018, 2023 | | 2023 |
| Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits F Stas, D Bol 2017 IEEE International Symposium on Circuits and Systems (ISCAS), 1-4, 2017 | | 2017 |
