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Since 2019
Citations
1
1
h-index
1
1
i10-index
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Aditya Anirudh Jonnalagadda
BITS Pilani
Verified email at hyderabad.bits-pilani.ac.in
VLSI Design
Approximate Computing
Computer Architecture
FPGA design
Deep Neural Networks
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Design of energy efficient posit multiplier
AA Jonnalagadda, AK Uppugunduru, S Veeramachaneni, SE Ahmed
Proceedings of the Great Lakes Symposium on VLSI 2023, 645-651
, 2023
1
2023
ADEPNET: A Dynamic-Precision Efficient Posit Multiplier for Neural Networks
AA Jonnalagadda, UA Kumar, R Thotli, S Sardesai, S Veeramachaneni, ...
IEEE Access 12, 31036-31046
, 2024
2024
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