Lars-Åke Ragnarsson
Lars-Åke Ragnarsson
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Ultrathin high-K gate stacks for advanced CMOS devices
EP Gusev, DA Buchanan, E Cartier, A Kumar, D DiMaria, S Guha, ...
International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001
Origin of NBTI variability in deeply scaled pFETs
B Kaczer, T Grasser, PJ Roussel, J Franco, R Degraeve, LA Ragnarsson, ...
2010 IEEE International Reliability Physics Symposium, 26-32, 2010
Electrical properties of high-κ gate dielectrics: Challenges, current issues, and possible solutions
M Houssa, L Pantisano, LÅ Ragnarsson, R Degraeve, T Schram, ...
Materials Science and Engineering: R: Reports 51 (4-6), 37-85, 2006
Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization
LÅ Ragnarsson, Z Li, J Tseng, T Schram, E Rohr, MJ Cho, T Kauerauf, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Atomic layer deposition method for depositing a layer
P Zimmerman, M Caymax, S De Gendt, A Delabie, LA Ragnarsson
US Patent 7,579,285, 2009
Method for manufacturing a semiconductor device comprising transistors each having a different effective work function
LA Ragnarsson, T Schram, HFW Dekkers, SA Chew
US Patent 9,287,273, 2016
High performance Ge pMOS devices using a Si-compatible process flow
P Zimmerman, G Nicholas, B De Jaeger, B Kaczer, A Stesmans, ...
2006 International Electron Devices Meeting, 1-4, 2006
Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession
T Chiarella, L Witters, A Mercha, C Kerner, M Rakowski, C Ortolland, ...
Solid-State Electronics 54 (9), 855-860, 2010
Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates
H Mertens, R Ritzenthaler, A Chasin, T Schram, E Kunnen, A Hikavyy, ...
2016 IEEE International Electron Devices Meeting (IEDM), 19.7. 1-19.7. 4, 2016
High temperature stability of dielectrics on Si: Interfacial metal diffusion and mobility degradation
S Guha, EP Gusev, H Okorn-Schmidt, M Copel, LÅ Ragnarsson, ...
Applied Physics Letters 81 (16), 2956-2958, 2002
Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs
J Franco, B Kaczer, M Toledano-Luque, PJ Roussel, J Mitard, ...
2012 IEEE International Reliability Physics Symposium (IRPS), 5A. 4.1-5A. 4.6, 2012
Molecular-beam-deposited yttrium-oxide dielectrics in aluminum-gated metal–oxide–semiconductor field-effect transistors: Effective electron mobility
LÅ Ragnarsson, S Guha, M Copel, E Cartier, NA Bojarczuk, J Karasinski
Applied Physics Letters 78 (26), 4169-4171, 2001
Electrical characterization of centers in structures: The influence of surface potential on passivation during post metallization anneal
LÅ Ragnarsson, P Lundgren
Journal of Applied Physics 88 (2), 938-942, 2000
Insight into N/PBTI mechanisms in sub-1-nm-EOT devices
M Cho, JD Lee, M Aoulaiche, B Kaczer, P Roussel, T Kauerauf, ...
IEEE Transactions on Electron Devices 59 (8), 2042-2048, 2012
Estimation of fixed charge densities in hafnium-silicate gate dielectrics
VS Kaushik, BJ O'Sullivan, G Pourtois, N Van Hoornick, A Delabie, ...
IEEE Transactions on Electron Devices 53 (10), 2627-2633, 2006
Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ALD HfO/sub 2/metal gate stacks under positive constant voltage stress
R Degraeve, T Kauerauf, M Cho, M Zahid, LA Ragnarsson, DP Brunco, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
Ultrathin EOT high-κ/metal gate devices for future technologies: Challenges, achievements and perspectives
LÅ Ragnarsson, T Chiarella, M Togo, T Schram, P Absil, T Hoffmann
Microelectronic Engineering 88 (7), 1317-1322, 2011
1.5× 10− 9 Ωcm2 Contact resistivity on highly doped Si: P using Ge pre-amorphization and Ti silicidation
H Yu, M Schaekers, E Rosseel, A Peter, JG Lee, WB Song, S Demuynck, ...
2015 IEEE International Electron Devices Meeting (IEDM), 21.7. 1-21.7. 4, 2015
Scaling to sub-1 nm equivalent oxide thickness with hafnium oxide deposited by atomic layer deposition
A Delabie, M Caymax, B Brijs, DP Brunco, T Conard, E Sleeckx, ...
Journal of the Electrochemical Society 153 (8), F180, 2006
Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier
NA Bojarczuk Jr, KK Chan, CP D'emic, E Gousev, S Guha, PC Jamison, ...
US Patent 6,891,231, 2005
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