A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20nm FinFET technologies M Ansari, H Afzali-Kusha, B Ebrahimi, Z Navabi, A Afzali-Kusha, ... INTEGRATION, the VLSI journal 50, 91-106, 2015 | 75 | 2015 |
Design Exploration of Energy-Efficient Accuracy-Configurable Dadda Multipliers With Improved Lifetime Based on Voltage Overscaling H Afzali-Kusha, M Vaeztourshizi, M Kamal, M Pedram IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (5 …, 2020 | 28 | 2020 |
Energy and Reliability Improvement of Voltage-Based, Clustered, Coarse-Grain Reconfigurable Architectures by Employing Quality-Aware Mapping H Afzali-Kusha, O Akbari, M Kamal, M Pedram IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (3 …, 2018 | 21 | 2018 |
Minimizing the energy-delay product of SRAM arrays using a device-circuit-architecture co-optimization framework A Shafaei, H Afzali-Kusha, M Pedram Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016 | 16 | 2016 |
Low power and robust 8T/10T subthreshold SRAM cells B Ebrahimi, H Afzali-Kusha, A Afzali-Kusha 2012 International Conference on Synthesis, Modeling, Analysis and …, 2012 | 15 | 2012 |
Low-power Accuracy-configurable Carry Look-ahead Adder Based on Voltage Overscaling Technique H Afzali-Kusha, M Kamal, M Pedram 2020 21st International Symposium on Quality Electronic Design (ISQED), 67-72, 2020 | 7 | 2020 |
Energy Consumption and Lifetime Improvement of Coarse-Grained Reconfigurable Architectures Targeting Low-Power Error-Tolerant Applications H Afzali-Kusha, O Akbari, M Kamal, M Pedram Proceedings of the 2018 on Great Lakes Symposium on VLSI, 431-434, 2018 | 7 | 2018 |
Workload and temperature dependent evaluation of BTI-induced lifetime degradation in digital circuits B Eghbalkhah, M Kamal, H Afzali-Kusha, A Afzali-Kusha, ... Microelectronics Reliability 55 (8), 1152-1162, 2015 | 7 | 2015 |
A 125mV 2ns-access-time 16Kb SRAM design based on a 6T hybrid TFET-FinFET cell H Afzali-Kusha, A Shafaei, M Pedram 2018 19th International Symposium on Quality Electronic Design (ISQED), 280-285, 2018 | 5 | 2018 |
High-performance and high-yield 5 nm underlapped FinFET SRAM design using P-type access transistors R Yarmand, B Ebrahimi, H Afzali-Kusha, A Afzali-Kusha, M Pedram Quality Electronic Design (ISQED), 2015 16th International Symposium on, 10-17, 2015 | 5 | 2015 |
X-NVDLA: Runtime Accuracy Configurable NVDLA Based on Applying Voltage Overscaling to Computing and Memory Units H Afzali-Kusha, M Pedram IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 | 3 | 2023 |
Optimizing the operating voltage of tunnel FET-based SRAM arrays equipped with read/write assist circuitry H Afzali-Kusha, A Shafaei, M Pedram Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 415-420, 2016 | 2 | 2016 |
X-NVDLA: Runtime Accuracy Configurable NVDLA based on Employing Voltage Overscaling Approach H Afzali-Kusha, M Pedram 2022 23rd International Symposium on Quality Electronic Design (ISQED), 7-12, 2022 | 1 | 2022 |
Design Techniques for Approximate Realization of Data-Flow Graphs M Vaeztourshizi, H Afzali-Kusha, M Kamal, M Pedram Approximate Computing, 175-206, 2022 | | 2022 |