| Rationale for a 3D heterogeneous multi-core processor E Rotenberg, BH Dwiel, E Forbes, Z Zhang, R Widialaksono, ... 2013 IEEE 31st International Conference on Computer Design (ICCD), 154-168, 2013 | 37 | 2013 |
| Post-silicon cpu adaptation made practical using machine learning SJ Tarsa, RBR Chowdhury, J Sebot, G Chinya, J Gaur, ... Proceedings of the 46th International Symposium on Computer Architecture, 14-26, 2019 | 27 | 2019 |
| AnyCore: A synthesizable RTL model for exploring and fabricating adaptive superscalar cores RBR Chowdhury, AK Kannepalli, S Ku, E Rotenberg 2016 IEEE International Symposium on Performance Analysis of Systems and …, 2016 | 25 | 2016 |
| Under 100-cycle thread migration latency in a single-isa heterogeneous multi-core processor E Forbes, Z Zhang, R Widialaksono, B Dwiel, RBR Chowdhury, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-1, 2015 | 14 | 2015 |
| Slipstream processors revisited: Exploiting branch sets V Srinivasan, RBR Chowdhury, E Rotenberg 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture …, 2020 | 12 | 2020 |
| H3 (Heterogeneity in 3D): A Logic-on-logic 3D-stacked Heterogeneous Multi-core Processor V Srinivasan, RBR Chowdhury, E Forbes, R Widialaksono, Z Zhang, ... 2017 IEEE International Conference on Computer Design (ICCD), 145-152, 2017 | 8 | 2017 |
| Experiences with two fabscalar-based chips E Forbes, RBR Chowdhury, B Dwiel, A Kannepalli, V Srinivasan, Z Zhang, ... 6th Workshop on Architectural Research Prototyping (WARP-6), 2015 | 8 | 2015 |
| QEI: Query acceleration can be generic and efficient in the cloud Y Yuan, Y Wang, R Wang, RBR Chowhury, C Tai, NS Kim 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 6 | 2021 |
| Physical design of a 3D-stacked heterogeneous multi-core processor R Widialaksono, RBR Chowdhury, Z Zhang, J Schabel, S Lipa, ... 2016 IEEE International 3D Systems Integration Conference (3DIC), 1-5, 2016 | 6 | 2016 |
| Diligent tlbs: a mechanism for exploiting heterogeneity in tlb miss behavior H Elnawawy, RBR Chowdhury, A Awad, GT Byrd Proceedings of the ACM International Conference on Supercomputing, 195-205, 2019 | 5 | 2019 |
| Inter-cluster communication of live-in register values S Pediaditaki, E Schuchman, RBR Chowdhury, M Shevgoor US Patent 10,437,590, 2019 | 4 | 2019 |
| AnyCore-1: A comprehensively adaptive 4-way superscalar processor. RBR Chowdhury, AK Kannepalli, E Rotenberg Hot Chips Symposium, 1, 2016 | 4 | 2016 |
| AnyCore: Design, Fabrication, and Evaluation of Comprehensively Adaptive Superscalar Processors RBR Chowdhury North Carolina State University, 2016 | 4 | 2016 |
| Design methodology internal sub state observer using CPLD J RoyChoudhury, TP Banerjee, A Nathvani, RBR Chowdhury, ... 2009 World Congress on Nature & Biologically Inspired Computing (NaBIC …, 2009 | 4 | 2009 |
| Translation table entry prefetching in dynamic binary translation based processor G Venkatasubramanian, JM Agron, C Pereira, G Hinton, S Winkel, ... US Patent App. 15/839,310, 2019 | 3 | 2019 |
| Variable-length instruction steering to instruction decode clusters M Azeem, RBR Chowdhury, X Zou, M Ahmadi, JJ Zajo, A Sabba, ... US Patent App. 17/712,139, 2023 | 2 | 2023 |
| Translation pinning in translation lookaside buffers RBR Chowdhury, H Elnawawy, A Awad US Patent App. 15/843,165, 2019 | 2 | 2019 |
| Practical post silicon cpu adaptation using machine learning S Tarsa, R Chowdhury, J Sebot, G Chinya, J Gaur, K Sankaranarayanan, ... ISCA, 2019 | 2 | 2019 |
| Fabscalarrisc-v RBR Chowdhury, AK Kannepalli, E Rotenberg 2nd RISC-V Workshop, 2015 | 2 | 2015 |
| Technology For Optimizing Memory-To-Register Operations VT Mekkat, SCA Winkel, RBR Chowdhury US Patent App. 17/304,775, 2022 | 1 | 2022 |
Eric RotenbergNorth Carolina State UniversityVerified email at ncsu.edu
