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Gabriel Weisz
Gabriel Weisz
Microsoft
Verified email at cs.cmu.edu - Homepage
Title
Cited by
Cited by
Year
A configurable cloud-scale DNN processor for real-time AI
J Fowers, K Ovtcharov, M Papamichael, T Massengill, M Liu, D Lo, ...
2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture …, 2018
4812018
Serving dnns in real time at datacenter scale with project brainwave
E Chung, J Fowers, K Ovtcharov, M Papamichael, A Caulfield, ...
iEEE Micro 38 (2), 8-20, 2018
2902018
GraphGen: An FPGA framework for vertex-centric graph computation
E Nurvitadhi, G Weisz, Y Wang, S Hurkat, M Nguyen, JC Hoe, JF Martínez, ...
2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom …, 2014
1502014
A configurable cloud-scale dnn processor for real-time ai. In 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA)
J Fowers, K Ovtcharov, M Papamichael, T Massengill, M Liu, D Lo, ...
IEEE. https://doi. org/10.1109/isca, 2018
532018
A study of pointer-chasing performance on shared-memory processor-FPGA systems
G Weisz, J Melber, Y Wang, K Fleming, E Nurvitadhi, JC Hoe
Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016
422016
Evaluating rapid application development with python for heterogeneous processor-based fpgas
AG Schmidt, G Weisz, M French
2017 IEEE 25th Annual International Symposium on Field-Programmable Custom …, 2017
352017
CoRAM++: Supporting data-structure-specific memory interfaces for FPGA computing
G Weisz, JC Hoe
2015 25th International conference on field programmable logic and …, 2015
282015
Neural network processor based on application specific synthesis specialization parameters
J Fowers, K Ovtcharov, ES Chung, TM Massengill, MG Liu, GL Weisz
US Patent App. 15/959,206, 2019
222019
Prototype and evaluation of the coram memory architecture for fpga-based computing
ES Chung, MK Papamichael, G Weisz, JC Hoe, K Mai
Proceedings of the ACM/SIGDA international symposium on Field Programmable …, 2012
212012
SpaceCubeX: A framework for evaluating hybrid multi-core CPU/FPGA/DSP architectures
AG Schmidt, G Weisz, M French, T Flatley, CY Villalpando
2017 IEEE Aerospace Conference, 1-10, 2017
172017
C-to-coram: Compiling perfect loop nests to the portable coram abstraction
G Weisz, JC Hoe
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
122013
High performance linkage disequilibrium: FPGAs hold the key
N Alachiotis, G Weisz
Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016
112016
Graphgen for coram: Graph computation on FPGAs
G Weisz, E Nurvitadhi, J Hoe
Workshop on the Intersections of Computer Architecture and Reconfigurable Logic, 2013
102013
Inside Project Brainwave's Cloud-Scale, Real-Time AI Processor
J Fowers, K Ovtcharov, MK Papamichael, T Massengill, M Liu, D Lo, ...
IEEE Micro 39 (3), 20-28, 2019
92019
Cross-platform FPGA accelerator development using CoRAM and CONNECT
ES Chung, MK Papamichael, G Weisz, JC Hoe
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
22013
Matrix vector multiplier with a vector register file comprising a multi-port memory
J Fowers, K Ovtcharov, ES Chung, TM Massengill, MG Liu, GL Weisz
US Patent 10,795,678, 2020
12020
Kermin Fleming (Intel)
A Dehon, A Koch, A Schmidt, B Rouhani, B Hutchings, C Plessl, C Bobda, ...
Publications Chair
J Szefer, A Schmidt, L Pozzi, X Guo, G Weisz, F Koushanfar, G Zgheib
FPGAs (ReConFig19) Keynote 2 Global-Scale FPGA-Accelerated Deep Learning Inference with Microsoft's Project Brainwave
G Weisz
Automated Compilation of ISPC Programs to FPGA
G Weisz
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