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Andrea Bandiziol
Andrea Bandiziol
Analog Mixed-Signal Designer, Infineon Technologies
Verified email at infineon.com
Title
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Cited by
Year
A TCAD-based methodology to model the site-binding charge at ISFET/electrolyte interfaces
A Bandiziol, P Palestri, F Pittino, D Esseni, L Selmi
IEEE Transactions on Electron Devices 62 (10), 3379-3386, 2015
932015
A CMOS pixelated nanocapacitor biosensor platform for high-frequency impedance spectroscopy and imaging
F Widdershoven, A Cossettini, C Laborde, A Bandiziol, PP van Swinderen, ...
IEEE transactions on biomedical circuits and systems 12 (6), 1369-1382, 2018
542018
A simple simulation approach for the estimation of convergence and performance of fully adaptive equalization in high-speed serial interfaces
D Menin, A De Prà, A Bandiziol, W Grollitsch, R Nonis, P Palestri
IEEE Transactions on Components, Packaging and Manufacturing Technology 9 …, 2019
92019
Design of a transmitter for high-speed serial interfaces in automotive micro-controller
A Bandiziol, W Grollitsch, F Brandonisio, R Nonis, P Palestri
2016 39th International Convention on Information and Communication …, 2016
92016
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm
A Bandiziol, W Grollitsch, F Brandonisio, M Bassi, R Nonis, P Palestri
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
82018
Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes
M Dazzi, P Palestri, D Rossi, A Bandiziol, I Loi, D Bellasi, L Benini
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
82018
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers
A Bandiziol, W Grollitsch, F Brandonisio, R Nonis, P Palestri
2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 321-324, 2016
82016
Design and simulation of a 12 Gb/s transceiver with 8-tap FFE, offset-compensated samplers and fully adaptive 1-tap speculative/3-tap DFE and sampling phase for MIPI A-PHY …
D Menin, A Bandiziol, W Grollitsch, R Nonis, P Palestri
IEEE Transactions on Circuits and Systems II: Express Briefs 67 (8), 1369-1373, 2019
72019
Analytical modeling of jitter in bang-bang CDR circuits featuring phase interpolation
P Palestri, A Elnaqib, D Menin, K Shyti, F Brandonisio, A Bandiziol, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (7 …, 2021
42021
Design and characterization of a 9.2-Gb/s transceiver for automotive microcontroller applications with 8-Taps FFE and 1-Tap unrolled/4-taps DFE
A Bandiziol, W Grollitsch, G Steffan, R Nonis, P Palestri
IEEE Transactions on Circuits and Systems II: Express Briefs 65 (10), 1305-1309, 2018
42018
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces
A Cortiula, M Dazzi, M Marcon, D Menin, M Scapol, A Bandiziol, ...
2019 42nd International Convention on Information and Communication …, 2019
32019
A Simple Modelling Tool for Fast Combined Simulation of Interconnections, Inter-Symbol Interference and Equalization in High-Speed Serial Interfaces for Chip-to-Chip Communications
D Menin, T Bernardi, A Cortiula, M Dazzi, AD Prà, M Marcon, M Scapol, ...
ADVANCES IN SCIENCE, TECHNOLOGY AND ENGINEERING SYSTEMS JOURNAL 5 (2), 527-536, 2020
22020
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers
D D'Ampolo, A Bandiziol, D Menin, W Grollitsch, R Nonis, P Palestri
2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 225-228, 2019
12019
2023 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 70
E Abbasian, A Abdelhafiz, BA Abdelmagid, DB Abdi, AA Abidi, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (12), 2023
2023
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces
A Cortiula, D Menin, A Bandiziol, W Grollitsch, R Nonis, P Palestri
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (2), 940-951, 2022
2022
2021 Index IEEE Transactions on Very Large Scale Integration (VLSI) Systems Vol. 29
M Akbari, A Akkaya, T Alan, ZIE Alaoui, A Alaql, M Alioto, A Aljuffri, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (12), 2021
2021
Characterization, Modeling and Design of a 10Gbps Serial Link
A Bandiziol
Università degli Studi di Udine, 2018
2018
System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics
A Bandiziol, W Grollitsch, F Brandonisio, R Nonis, P Palestri
2017 13th Conference on Ph. D. Research in Microelectronics and Electronics …, 2017
2017
System and transistor level analysis of an 8-taps FFE 10Gbps serial link transmitter with realistic channels and supply parasitics
P PALESTRI, A BANDIZIOL
PRIME 2017, Giardini Naxos–Taormina, Italy
A Abou Khalil, T Addabbo, G Adinolfi, A Akdikmen, T Al-Attar, B Al-Qudsi, ...
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