| DSIP: A scalable inference accelerator for convolutional neural networks J Jo, S Cha, D Rho, IC Park IEEE Journal of Solid-State Circuits 53 (2), 605-618, 2017 | 71 | 2017 |
| Energy-efficient convolution architecture based on rescheduled dataflow J Jo, S Kim, IC Park IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4196-4207, 2018 | 61 | 2018 |
| Energy-efficient floating-point MFCC extraction architecture for speech recognition systems J Jo, H Yoo, IC Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 754-758, 2015 | 53 | 2015 |
| Area-efficient multimode encoding architecture for long BCH codes H Yoo, J Jung, J Jo, IC Park IEEE Transactions on Circuits and Systems II: Express Briefs 60 (12), 872-876, 2013 | 35 | 2013 |
| A 2.74-pJ/bit, 17.7-Gb/s iterative concatenated-BCH decoder in 65-nm CMOS for NAND flash memory Y Lee, H Yoo, J Jung, J Jo, IC Park IEEE journal of solid-state circuits 48 (10), 2531-2540, 2013 | 33 | 2013 |
| Low-complexity low-latency architecture for matching of data encoded with hard systematic error-correcting codes BY Kong, J Jo, H Jeong, M Hwang, S Cha, B Kim, IC Park IEEE Transactions on Very Large Scale Integration (VLSI) Systems 22 (7 …, 2013 | 29 | 2013 |
| Modified Viterbi Scoring for HMM-Based Speech Recognition. J Jo, HG Kim, IC Park, BC Jung, H Yoo Intelligent Automation & Soft Computing 25 (2), 2019 | 12 | 2019 |
| Hybrid convolution architecture for energy-efficient deep neural network processing S Kim, J Jo, IC Park IEEE Transactions on Circuits and Systems I: Regular Papers 68 (5), 2017-2029, 2021 | 4 | 2021 |
| Unidirectional Ring Ethernet and Media Access Controller with Automatic Relaying for Low-complexity In-vehicle Control Network I Yoo, J Jo, Y Ju, IC Park Journal of Semiconductor Technology and Science 17 (5), 697-708, 2017 | 1 | 2017 |
| Low-latency low-cost architecture for square and cube roots J Jo, IC Park IEICE Transactions on Fundamentals of Electronics, Communications and …, 2017 | 1 | 2017 |
