Esteban J. Garzón C.
Esteban J. Garzón C.
Ph.D. in Electronics Engineering, DIMES, University of Calabria
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Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework
E Garzón, R De Rose, F Crupi, L Trojman, M Lanuzza
Microelectronic Engineering 215, 111009, 2019
Exploiting STT-MRAMs for cryogenic non-volatile cache applications
E Garzón, R De Rose, F Crupi, A Teman, M Lanuzza
IEEE Transactions on Nanotechnology 20, 123-128, 2021
Assessment of STT-MRAMs based on double-barrier MTJs for cache applications by means of a device-to-system level simulation framework
E Garzon, R De Rose, F Crupi, L Trojman, G Finocchio, M Carpentieri, ...
Integration 71, 56-69, 2020
Gain-cell embedded DRAM under cryogenic operation—A first study
E Garzón, Y Greenblatt, O Harel, M Lanuzza, A Teman
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (7 …, 2021
Simulation analysis of DMTJ-based STT-MRAM operating at cryogenic temperatures
E Garzón, R De Rose, F Crupi, M Carpentieri, A Teman, M Lanuzza
IEEE Transactions on Magnetics 57 (7), 1-6, 2021
Reconfigurable CMOS/STT-MTJ non-volatile circuit for logic-in-memory applications
E Garzón, B Zambrano, T Moposita, R Taco, LM Prócel, L Trojman
2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020
Ultralow voltage finFET-versus TFET-based STT-MRAM cells for IoT applications
E Garzón, M Lanuzza, R Taco, S Strangio
Electronics 10 (15), 1756, 2021
Exploiting Double-Barrier MTJs for Energy-Efficient Nanoscaled STT-MRAMs
E Garzón, R De Rose, F Crupi, L Trojman, G Finocchio, M Carpentieri, ...
2019 16th International Conference on Synthesis, Modeling, Analysis and …, 2019
Relaxing non-volatility for energy-efficient DMTJ based cryogenic STT-MRAM
E Garzon, R De Rose, F Crupi, L Trojman, A Teman, M Lanuzza
Solid-State Electronics 184, 108090, 2021
Embedded memories for cryogenic applications
E Garzón, A Teman, M Lanuzza
Electronics 11 (1), 61, 2021
A 0.05 mm², 350 mV, 14 nW Fully-Integrated Temperature Sensor in 180-nm CMOS
B Zambrano, E Garzón, S Strangio, F Crupi, M Lanuzza
IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 749-753, 2021
Energy Efficient Self-Adaptive Dual Mode Logic Address Decoder
K Vicuña, C Mosquera, A Musello, S Benedictis, M Rendón, E Garzón, ...
Electronics 10 (9), 1052, 2021
Space-time diversity for NLOS mitigation in TDOA-based positioning systems
ER Játiva, E Garzón, J Vidal
2016 IEEE International Engineering Summit, II Cumbre Internacional de las …, 2016
Hamming distance tolerant content-addressable memory (hd-cam) for dna classification
E Garzón, R Golman, Z Jahshan, R Hanhan, N Vinshtok-Melnik, ...
IEEE Access 10, 28080-28093, 2022
A 0.6 V–1.8 V Compact Temperature Sensor with 0.24° C Resolution,±1.4° C Inaccuracy and 1.06 nJ per Conversion
B Zambrano, E Garzón, S Strangio, G Iannaccone, M Lanuzza
IEEE Sensors Journal, 2022
Voltage and Technology Scaling of DMTJ-based STT-MRAMs for Energy-Efficient Embedded Memories
E Garzón, R Taco, LM Prócel, L Trojman, M Lanuzza
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 01-04, 2022
Field-Free Magnetic Tunnel Junction for Logic Operations Based on Voltage-Controlled Magnetic Anisotropy
F Cutugno, E Garzón, R De Rose, G Finocchio, M Lanuzza, M Carpentieri
IEEE Magnetics Letters 12, 1-4, 2021
Device-to-System Level Simulation Framework for STT-DMTJ Based Cache Memory
E Garzón, R De Rose, F Crupi, M Lanuzza
2019 26th IEEE International Conference on Electronics, Circuits and Systems …, 2019
Microprocessor Design with a Direct Bluetooth Connection in 45 nm Technology Using Microwind
E Garzon, F Chavez, D Jaramillo, L Sanchez, S Lara, C Macias, E Acurio, ...
2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 105-108, 2019
Fast computation of cramer-rao bounds for toa
E Garzón, S Valdiviezo, R Játiva, J Vidal
2016 IEEE Latin American Conference on Computational Intelligence (LA-CCI), 1-6, 2016
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