| UNPU: An energy-efficient deep neural network accelerator with fully variable weight bit precision J Lee, C Kim, S Kang, D Shin, S Kim, HJ Yoo IEEE Journal of Solid-State Circuits 54 (1), 173-185, 2018 | 301 | 2018 |
| UNPU: A 50.6 TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision J Lee, C Kim, S Kang, D Shin, S Kim, HJ Yoo 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 218-220, 2018 | 284 | 2018 |
| 14.6 A 0.62 mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detector K Bong, S Choi, C Kim, S Kang, Y Kim, HJ Yoo 2017 IEEE International Solid-State Circuits Conference (ISSCC), 248-249, 2017 | 176 | 2017 |
| 7.4 GANPU: A 135TFLOPS/W multi-DNN training processor for GANs with speculative dual-sparsity exploitation S Kang, D Han, J Lee, D Im, S Kim, S Kim, HJ Yoo 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 140-142, 2020 | 61 | 2020 |
| A 2.1 TFLOPS/W mobile deep RL accelerator with transposable PE array and experience compression C Kim, S Kang, D Shin, S Choi, Y Kim, HJ Yoo 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 136-138, 2019 | 54 | 2019 |
| DT-CNN: Dilated and transposed convolution neural network accelerator for real-time image segmentation on mobile devices D Im, D Han, S Choi, S Kang, HJ Yoo 2019 IEEE international symposium on circuits and systems (ISCAS), 1-5, 2019 | 46 | 2019 |
| The hardware and algorithm co-design for energy-efficient DNN processor on edge/mobile devices J Lee, S Kang, J Lee, D Shin, D Han, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (10), 3458-3470, 2020 | 39 | 2020 |
| A full HD 60 fps CNN super resolution processor with selective caching based layer fusion for mobile devices J Lee, D Shin, J Lee, J Lee, S Kang, HJ Yoo 2019 Symposium on VLSI Circuits, C302-C303, 2019 | 34 | 2019 |
| DT-CNN: An energy-efficient dilated and transposed convolutional neural network processor for region of interest based image segmentation D Im, D Han, S Choi, S Kang, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (10), 3471-3483, 2020 | 33 | 2020 |
| GANPU: An energy-efficient multi-DNN training processor for GANs with speculative dual-sparsity exploitation S Kang, D Han, J Lee, D Im, S Kim, S Kim, J Ryu, HJ Yoo IEEE Journal of Solid-State Circuits 56 (9), 2845-2857, 2021 | 29 | 2021 |
| A power-efficient CNN accelerator with similar feature skipping for face recognition in mobile devices S Kim, J Lee, S Kang, J Lee, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 67 (4), 1181-1193, 2020 | 27 | 2020 |
| B-Face: 0.2 mW CNN-based face recognition processor with face alignment for mobile user identification S Kang, J Lee, C Kim, HJ Yoo 2018 IEEE symposium on VLSI circuits, 137-138, 2018 | 27 | 2018 |
| A 146.52 TOPS/W deep-neural-network learning processor with stochastic coarse-fine pruning and adaptive input/output/weight skipping S Kim, J Lee, S Kang, J Lee, HJ Yoo 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 24 | 2020 |
| Low-power scalable 3-d face frontalization processor for cnn-based face recognition in mobile devices S Kang, J Lee, K Bong, C Kim, Y Kim, HJ Yoo IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (4 …, 2018 | 18 | 2018 |
| UNPU: A 50.6 TOPS/W unified deep neural network accelerator with 1b-to-16b fully-variable weight bit-precision. In 2018 IEEE International Solid-State Circuits Conference-(ISSCC) J Lee, C Kim, S Kang, D Shin, S Kim, HJ Yoo IEEE 6, 218-220, 2018 | 15 | 2018 |
| An overview of sparsity exploitation in CNNs for on-device intelligence with software-hardware cross-layer optimizations S Kang, G Park, S Kim, S Kim, D Han, HJ Yoo IEEE Journal on Emerging and Selected Topics in Circuits and Systems 11 (4 …, 2021 | 13 | 2021 |
| PNPU: An energy-efficient deep-neural-network learning processor with stochastic coarse–fine level weight pruning and adaptive input/output/weight zero skipping S Kim, J Lee, S Kang, J Lee, W Jo, HJ Yoo IEEE Solid-State Circuits Letters 4, 22-25, 2020 | 13 | 2020 |
| A 4.45 ms low-latency 3D point-cloud-based neural network processor for hand pose estimation in immersive wearable devices D Im, S Kang, D Han, S Choi, HJ Yoo 2020 IEEE Symposium on VLSI Circuits, 1-2, 2020 | 12 | 2020 |
| DSPU: A 281.6 mW real-time depth signal processing unit for deep learning-based dense RGB-D data acquisition with depth fusion and 3D bounding box extraction in mobile platforms D Im, G Park, Z Li, J Ryu, S Kang, D Han, J Lee, HJ Yoo 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 510-512, 2022 | 9 | 2022 |
| Tsunami: Triple sparsity-aware ultra energy-efficient neural network training accelerator with multi-modal iterative pruning S Kim, J Lee, S Kang, D Han, W Jo, HJ Yoo IEEE Transactions on Circuits and Systems I: Regular Papers 69 (4), 1494-1506, 2022 | 9 | 2022 |
