| CAP-RAM: A charge-domain in-memory computing 6T-SRAM for accurate and precision-programmable CNN inference Z Chen, Z Yu, Q Jin, Y He, J Wang, S Lin, D Li, Y Wang, K Yang IEEE Journal of Solid-State Circuits 56 (6), 1924-1935, 2021 | 61 | 2021 |
| A 1.2-V 2.41-GHz three-stage CMOS OTA with efficient frequency compensation technique S Liu, Z Zhu, J Wang, L Liu, Y Yang IEEE Transactions on Circuits and Systems I: Regular Papers 66 (1), 20-30, 2018 | 36 | 2018 |
| Low-power single-ended SAR ADC using symmetrical DAC switching for image sensors with passive CDS and PGA technique J Wang, S Liu, Y Shen, Z Zhu IEEE Transactions on Circuits and Systems I: Regular Papers 65 (8), 2378-2388, 2018 | 25 | 2018 |
| A 10-bit self-clocked SAR ADC with enhanced energy efficiency for multi-sensor applications S Liu, Y Shen, J Wang, Z Zhu IEEE Sensors Journal 18 (10), 4223-4233, 2018 | 20 | 2018 |
| A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage J Wang, Z Zhu, S Liu, R Ding Microelectronics Journal 64, 86-91, 2017 | 20 | 2017 |
| MC2-RAM: An In-8T-SRAM Computing Macro Featuring Multi-Bit Charge-Domain Computing and ADC-Reduction Weight Encoding Z Chen, Q Jin, J Wang, Y Wang, K Yang 2021 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2021 | 11 | 2021 |
| A 10-bit reconfigurable ADC with SAR/SS mode for neural recording J Wang, Y Hua, Z Zhu Analog Integrated Circuits and Signal Processing 101, 297-305, 2019 | 11 | 2019 |
| A 0.6-V 9-bit 1-MS/s charging sharing SAR ADC with judging-window switching logic and independent reset comparator for power-effective applications J Wang, Z Zhu IEEE Transactions on Circuits and Systems II: Express Briefs 67 (10), 1750-1754, 2019 | 10 | 2019 |
| High input impedance low-noise CMOS analog frontend IC for wearable electrocardiogram monitoring C Zhang, J Wang, L Wang, L Liu, Y Li, Z Zhu IEEE Transactions on Circuits and Systems II: Express Briefs 67 (7), 1169-1173, 2019 | 10 | 2019 |
| A low-power low-noise amplifier with fully self-biased feedback loop structure for neural recording X Zhang, J Wang, Z Zhu Analog Integrated Circuits and Signal Processing 99, 199-208, 2019 | 10 | 2019 |
| An improved-linearity, single-stage variable-gain amplifier using current squarer for wider gain range J Wang, Z Zhu Circuits, Systems, and Signal Processing 35 (12), 4550-4566, 2016 | 8 | 2016 |
| A Compact High-Performance Programmable-Gain Analog Front End for HomePlug AV2 Communication in 0.18- CMOS Z Zhu, J Wang IEEE Transactions on Circuits and Systems I: Regular Papers 64 (11), 2858-2870, 2017 | 4 | 2017 |
| A low distortion bootstrapped switch for 4-Bit MDAC Z Zhu, G Yu, J Wang, Y Yang Journal of Circuits, Systems and Computers 22 (01), 1250074, 2013 | 3 | 2013 |
| A 5 Gb/s CMOS adaptive equalizer for serial link H Wu, J Wang, H Liu Journal of Semiconductors 39 (4), 045003, 2018 | 2 | 2018 |
| A low distortion CMOS analogue switch with high-order compensation M Liu, J Wang, Z Zhu, W Guo, L Liu, R Ding Analog Integrated Circuits and Signal Processing 82, 495-500, 2015 | 2 | 2015 |
| A fast-locking, low-jitter pulsewidth control loop for high-speed ADC Z Zhu, M Liu, J Wang, Y Yang IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2013 | 2 | 2013 |
| CDS Circuit with High-Performance VGA Functionality and Its Design Procedure H Zhuang, Z Zhu, J Wang, Y Yang Circuits, Systems, and Signal Processing 36, 1781-1805, 2017 | | 2017 |
