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Reza Ghanaatian
Reza Ghanaatian
EPFL, Telecommunications Circuits Laboratory
Verified email at epfl.ch - Homepage
Title
Cited by
Cited by
Year
LoRa digital receiver analysis and implementation
R Ghanaatian, O Afisiadis, M Cotting, A Burg
ICASSP 2019-2019 IEEE International Conference on Acoustics, Speech and …, 2019
942019
A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing
R Ghanaatian, A Balatsoukas-Stimming, TC Müller, M Meidlinger, G Matz, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (2), 329-340, 2018
742018
A fully-unrolled LDPC decoder based on quantized message passing
A Balatsoukas-Stimming, M Meidlinger, R Ghanaatian, G Matz, A Burg
2015 IEEE Workshop on Signal Processing Systems (SiPS), 1-6, 2015
432015
Feedback-Aware Precoding for Millimeter Wave Massive MIMO Systems
R Ghanaatian, V Jamali, A Burg, R Schober
2019 IEEE 30th Annual International Symposium on Personal, Indoor and Mobile …, 2019
62019
A high-throughput VLSI architecture for real-time optical OFDM systems with an efficient phase equalizer
R Ghanaatian, M Shabany, MH Shoreh
Canadian Journal of Electrical and Computer Engineering 37 (2), 86-93, 2014
62014
A low-power correlator for wakeup receivers with algorithm pruning through early termination
R Ghanaatian, PN Whatmough, J Constantin, A Teman, A Burg
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2667-2670, 2016
22016
Channel estimation and iterative equalization for long-haul coherent optical OFDM communication systems
MH Shoreh, R Ghanaatian, JA Salehi
2015 13th International Conference on Telecommunications (ConTEL), 1-5, 2015
22015
Design for Test With Unreliable Memories by Restoring the Beauty of Randomness
R Ghanaatian, M Widmer, A Burg
IEEE Design & Test 39 (2), 112-120, 2021
12021
DVFS based power management for LDPC decoders with early termination
R Ghanaatian, A Burg
2017 IEEE International Workshop on Signal Processing Systems (SiPS), 1-6, 2017
12017
Method For Reading And Writing Unreliable Memories And A Corresponding Memory Controller Device and Memory
A Burg, R Ghanaatian
US Patent App. 17/482,594, 2022
2022
ErgoDEC: A Fault Tolerant 28 nm LDPC Decoder Providing Stable FER Quality with Unreliable Memories
R Ghanaatian Jahromi, R Giterman, A Bonetti, AP Burg
2022
Energy-and Cost-Efficient VLSI DSP Systems Design with Approximate Computing
R Ghanaatian Jahromi
EPFL, 2020
2020
An efficient high-throughput VLSI architecture for a synchronization block applied to real-time optical OFDM systems
R Ghanaatian, M Shabany, M Sharifkhani
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 1752-1755, 2014
2014
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