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Shrikanth Ganapathy
Shrikanth Ganapathy
Rivos Inc.
Verified email at rivosinc.com
Title
Cited by
Cited by
Year
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU
N Jing, Y Shen, Y Lu, S Ganapathy, Z Mao, M Guo, R Canal, X Liang
ACM SIGARCH Computer Architecture News 41 (3), 344-355, 2013
812013
Mitigating the impact of faults in unreliable memories for error-resilient applications
S Ganapathy, G Karakonstantis, A Teman, A Burg
2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2015
402015
Circuit propagation delay estimation through multivariate regression-based modeling under spatio-temporal variability
S Ganapathy, R Canal, A Gonzalez, A Rubio
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
352010
On characterizing near-threshold SRAM failures in FinFET technology
S Ganapathy, J Kalamatianos, K Kasprak, S Raasch
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
272017
Approximate computing with unreliable dynamic memories
S Ganapathy, A Teman, R Giterman, A Burg, G Karakonstantis
2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 1-4, 2015
272015
Impact of positive bias temperature instability (PBTI) on 3T1D-DRAM cells
N Aymerich, S Ganapathy, A Rubio, R Canal, A Gonzalez
Proceedings of the 21st edition of the great lakes symposium on Great lakes …, 2011
182011
A novel variation-tolerant 4T-DRAM cell with enhanced soft-error tolerance
S Ganapathy, R Canal, E Costenaro, D Alexandrescu, A Gonzalez, ...
2012 IEEE 30th International Conference on Computer Design (ICCD), 472-477, 2012
142012
Assessing the effects of low voltage in branch prediction units
A Chatzidimitriou, G Papadimitriou, D Gizopoulos, S Ganapathy, ...
2019 IEEE International Symposium on Performance Analysis of Systems and …, 2019
112019
On the concept of simultaneous execution of multiple applications on hierarchically based cluster and the silicon operating system
N Venkateswaran, VK Elangovan, K Ganesan, TPRS Sagar, ...
2008 IEEE International Symposium on Parallel and Distributed Processing, 1-8, 2008
112008
iRMW: A low-cost technique to reduce NBTI-dependent parametric failures in L1 data caches
S Ganapathy, R Canal, A González, A Rubio
2014 IEEE 32nd International Conference on Computer Design (ICCD), 68-74, 2014
92014
Informer: An integrated framework for early-stage memory robustness analysis
S Ganapathy, R Canal, D Alexandrescu, E Costenaro, A González, ...
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-4, 2014
92014
Variability-aware design space exploration of embedded memories
S Ganapathy, G Karakonstantis, R Canal, AP Burg
2014 IEEE 28th Convention of Electrical & Electronics Engineers in Israel …, 2014
82014
Killi: Runtime fault classification to deploy low voltage caches without MBIST
S Ganapathy, J Kalamatianos, BM Beckmann, S Raasch, LG Szafaryn
2019 IEEE International Symposium on High Performance Computer Architecture …, 2019
72019
Analysis and characterization of ultra low power branch predictors
A Chatzidimitriou, G Papadimitriou, D Gizopoulos, S Ganapathy, ...
2018 IEEE 36th International Conference on Computer Design (ICCD), 144-147, 2018
72018
Effectiveness of Hybrid Recovery Techniques on Parametric Failures
S Ganapathy, R Canal, A Gonzalez, A Rubio
International Symposium on Quality Electronic Design (ISQED'13), 2013
72013
Dynamic fine-grain body biasing of caches with latency and leakage 3T1D-based monitors
S Ganapathy, R Canal, A Gonzalez, A Rubio
2011 IEEE 29th International Conference on Computer Design (ICCD), 332-338, 2011
62011
Modest: a model for energy estimation under spatio-temporal variability
S Ganapathy, R Canal, A Gonzalez, A Rubio
2010 ACM/IEEE International Symposium on Low-Power Electronics and Design …, 2010
42010
Energy vs. reliability trade-offs exploration in biomedical ultra-low power devices
L Duch, PG Del Valle, S Ganapathy, A Burg, D Atienza
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 838-841, 2016
22016
Reliability in the face of variability in nanometer embedded memories
S Ganapathy
Universitat Politècnica de Catalunya, 2014
22014
Method and apparatus for using compression to improve performance of low voltage caches
J Kalamatianos, S Ganapathy, S Das, M Tomei
US Patent 10,884,940, 2021
12021
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