Gabriele Manganaro

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	All	Since 2019
Citations	2425	686
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i10-index	44	14

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Co-authors

luigi fortunaprofessor of system theory university of catania- Associate CNR IASI RomeVerified email at diees.unict.it
Paolo ArenaFull Professor of Automatic Control and BioroboticsVerified email at unict.it
Salvo BaglioUniversity of CataniaVerified email at unict.it
Riccardo CaponettoUniversity of Messina- Dipartimento di IngegneriaVerified email at unime.it
Jose Pineda de GyvezNXP Semiconductors and Eindhoven University of TechnologyVerified email at tue.nl
Franco MalobertiProfessor of Electronics; Pavia UniversityVerified email at unipv.it
Eric OtteWHOOPVerified email at whoop.com
Jaehun JeongBroadcom, Irvine, CAVerified email at umich.edu
Edoardo BonizzoniAssociate Professor, University of PaviaVerified email at unipv.it
maria gabriella xibiliaassociate professor of Automatic Control, University of Messina, ItalyVerified email at unime.it
Hajime ShibataAnalog DevicesVerified email at analog.com
Domine.M.W. LeenaertsVerified email at chello.nl
Filip TavernierAssociate professor, KU Leuven ESAT-MICAS, BelgiumVerified email at kuleuven.be
Piero MalcovatiUniversity of PaviaVerified email at unipv.it
SeongHwan ChoKAISTVerified email at ee.kaist.ac.kr
Athanasios RamkajSerDes Analog/Mixed-Signal Design | AMDVerified email at amd.com
Anantha ChandrakasanDean of Engineering, Massachusetts Institute of TechnologyVerified email at mit.edu
Rishabh MittalMediatek USA, formerly at MITVerified email at mit.edu
Giuseppe NunnariProfessor of Automatic Control and Industrial Automation, Università degli Studi di CataniaVerified email at dieei.unict.it
Luigi OcchipintiUniversity of CambridgeVerified email at eng.cam.ac.uk

Gabriele Manganaro

Director of Technology, MediaTek, Woburn, MA, USA

Verified email at mediatek.com

Data Converters ADC DAC PLL mixed-signal IC design


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A 12-b 10-GS/s interleaved pipeline ADC in 28-nm CMOS technology S Devarajan, L Singer, D Kelly, T Pan, J Silva, J Brunsilius, D Rey-Losada, ... IEEE Journal of Solid-State Circuits 52 (12), 3204-3218, 2017	229	2017
Chua's circuit can be generated by CNN cells P Arena, S Baglio, L Fortuna, G Manganaro IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 1995	224	1995
Cellular neural networks: chaos, complexity and VLSI processing G Manganaro, P Arena, L Fortuna Springer Science & Business Media, 2012	211	2012
A 14-b 100-MS/s pipelined ADC with a merged SHA and first MDAC BG Lee, BM Min, G Manganaro, JW Valvano IEEE Journal of Solid-State Circuits 43 (12), 2613-2619, 2008	132	2008
Generation of n‐double scrolls via cellular neural networks P Arena, S Baglio, L Fortuna, G Manganaro International Journal of circuit theory and applications 24 (3), 241-252, 1996	132	1996
Advanced data converters G Manganaro Cambridge University Press, 2011	119	2011
Hyperchaos from cellular neural networks P Arena, S Baglio, L Fortuna, G Manganaro Electronics letters 31 (4), 250-251, 1995	109	1995
Self-organization in a two-layer CNN P Arena, S Baglio, L Fortuna, G Manganaro IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 1998	108	1998
A 12 mW low power continuous-time bandpass ΔΣ modulator with 58 dB SNDR and 24 MHz bandwidth at 200 MHz IF H Chae, J Jeong, G Manganaro, MP Flynn IEEE Journal of Solid-State Circuits 49 (2), 405-415, 2013	68	2013
A 14b 100MS/s pipelined ADC with a merged active S/H and first MDAC BG Lee, BM Min, G Manganaro, JW Valvano 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008	58	2008
DNA computing based on chaos G Manganaro, JP De Gyvez Proceedings of 1997 IEEE International Conference on Evolutionary …, 1997	53	1997
State controlled CNN: A new strategy for generating high complex dynamics P ARENA, S BAGLIO, L FORTUNA, G MANGANARO IEICE transactions on fundamentals of electronics, communications and …, 1996	52	1996
Cellular neural networks to explore complexity P Arena, R Caponetto, L Fortuna, G Manganaro Soft Computing 1, 120-136, 1997	51	1997
A 12mW low-power continuous-time bandpass ΔΣ modulator with 58dB SNDR and 24MHz bandwidth at 200MHz IF H Chae, J Jeong, G Manganaro, M Flynn 2012 IEEE International Solid-State Circuits Conference, 148-150, 2012	46	2012
Feed-forward approach for timing skew in interleaved and double-sampled circuits G Manganaro US Patent 6,570,410, 2003	44	2003
40 MHz IF 1 MHz bandwidth two-path bandpass ΣΔ modulator with 72 dB DR consuming 16 mW I Galdi, E Bonizzoni, P Malcovati, G Manganaro, F Maloberti IEEE Journal of Solid-State Circuits 43 (7), 1648-1656, 2008	42	2008
A dual 10-b 200-MSPS pipelined D/A converter with DLL-based clock synthesizer G Manganaro, SU Kwak, AR Bugeja IEEE Journal of Solid-State Circuits 39 (11), 1829-1838, 2004	32	2004
16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving− 161dBFS/Hz NSD H Shibata, V Kozlov, Z Ji, A Ganesan, H Zhu, D Paterson 2017 IEEE International Solid-State Circuits Conference (ISSCC), 278-279, 2017	30	2017
Interleaving adcs: Unraveling the mysteries G Manganaro, D Robertson Analog Dialogue 49 (7), 2015	28	2015
Advances in analog and RF IC design for wireless communication systems G Manganaro, DMW Leenaerts Academic Press, 2013	28	2013

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