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John Sartori
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Slack redistribution for graceful degradation under voltage overscaling
AB Kahng, S Kang, R Kumar, J Sartori
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 825-831, 2010
2232010
Scalable stochastic processors
S Narayanan, J Sartori, R Kumar, DL Jones
2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010
1922010
Designing a processor from the ground up to allow voltage/reliability tradeoffs
AB Kahng, S Kang, R Kumar, J Sartori
HPCA-16 2010 The Sixteenth International Symposium on High-Performance …, 2010
1402010
Branch and data herding: Reducing control and memory divergence for error-tolerant GPU applications
J Sartori, R Kumar
Proceedings of the 21st international conference on Parallel architectures …, 2012
1142012
On the efficacy of NBTI mitigation techniques
TB Chan, J Sartori, P Gupta, R Kumar
2011 Design, Automation & Test in Europe, 1-6, 2011
842011
Statistical analysis and modeling for error composition in approximate computation circuits
WTJ Chan, AB Kahng, S Kang, R Kumar, J Sartori
2013 IEEE 31st international conference on computer design (ICCD), 47-53, 2013
812013
Low-power, low-storage-overhead chipkill correct via multi-line error correction
X Jian, H Duwe, J Sartori, V Sridharan, R Kumar
Proceedings of the International Conference on High Performance Computing …, 2013
722013
Approximate communication: Techniques for reducing communication bottlenecks in large-scale parallel systems
F Betzel, K Khatamifard, H Suresh, DJ Lilja, J Sartori, U Karpuzcu
ACM Computing Surveys (CSUR) 51 (1), 1-32, 2018
672018
Stochastic computing: embracing errors in architectureand design of processors and applications
J Sartori, J Sloan, R Kumar
Proceedings of the 14th international conference on compilers, architectures …, 2011
662011
Distributed peak power management for many-core architectures
J Sartori, R Kumar
2009 Design, Automation & Test in Europe Conference & Exhibition, 1556-1559, 2009
662009
Recovery-driven design: A power minimization methodology for error-tolerant processor modules
AB Kahng, S Kang, R Kumar, J Sartori
Proceedings of the 47th Design Automation Conference, 825-830, 2010
652010
Low-overhead, high-speed multi-core barrier synchronization
J Sartori, R Kumar
International Conference on High-Performance Embedded Architectures and …, 2010
652010
Power balanced pipelines
J Sartori, B Ahrens, R Kumar
IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012
572012
Exploiting dynamic timing slack for energy efficiency in ultra-low-power embedded systems
H Cherupalli, R Kumar, J Sartori
ACM SIGARCH Computer Architecture News 44 (3), 671-681, 2016
562016
Enhancing the efficiency of energy-constrained DVFS designs
AB Kahng, S Kang, R Kumar, J Sartori
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21 (10 …, 2012
492012
Variation-aware speed binning of multi-core processors
J Sartori, A Pant, R Kumar, P Gupta
2010 11th International Symposium on Quality Electronic Design (ISQED), 307-314, 2010
472010
Designing a cost-effective cache replacement policy using machine learning
S Sethumurugan, J Yin, J Sartori
2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021
412021
Bespoke processors for applications with ultra-low area and power constraints
H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori
Proceedings of the 44th Annual International Symposium on Computer …, 2017
352017
Architecting processors to allow voltage/reliability tradeoffs
J Sartori, R Kumar
Proceedings of the 14th international conference on Compilers, architectures …, 2011
322011
Determining application-specific peak power and energy requirements for ultra-low-power processors
H Cherupalli, H Duwe, W Ye, R Kumar, J Sartori
ACM Transactions on Computer Systems (TOCS) 35 (3), 1-33, 2017
312017
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