| Hardware architecture and software stack for PIM based on commercial DRAM technology: Industrial product S Lee, S Kang, J Lee, H Kim, E Lee, S Seo, H Yoon, S Lee, K Lim, H Shin, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 160 | 2021 |
| 25.4 a 20nm 6gb function-in-memory dram, based on hbm2 with a 1.2 tflops programmable computing unit using bank-level parallelism, for machine learning applications YC Kwon, SH Lee, J Lee, SH Kwon, JM Ryu, JP Son, O Seongil, HS Yu, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 350-352, 2021 | 134 | 2021 |
| Sparsity-aware and re-configurable NPU architecture for Samsung flagship mobile SoC JW Jang, S Lee, D Kim, H Park, AS Ardestani, Y Choi, C Kim, Y Kim, H Yu, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 76 | 2021 |
| Method and system for dynamically parallelizing application program SW Lee, SH Lee, DI Kang, M Kang US Patent 8,650,384, 2014 | 76 | 2014 |
| Quantization for rapid deployment of deep neural networks JH Lee, S Ha, S Choi, WJ Lee, S Lee arXiv preprint arXiv:1810.05488, 2018 | 52 | 2018 |
| 9.5 A 6K-MAC feature-map-sparsity-aware neural processing unit in 5nm flagship mobile SoC JS Park, JW Jang, H Lee, D Lee, S Lee, H Jung, S Lee, S Kwon, K Jeong, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 152-154, 2021 | 48 | 2021 |
| Method and apparatus for migrating task in multicore platform S Lee US Patent 9,135,060, 2015 | 42 | 2015 |
| On the construction of a powerful distributed authentication server without additional key management SM Hong, S Lee, Y Park, Y Cho, H Yoon Computer Communications 23 (17), 1638-1644, 2000 | 37 | 2000 |
| Method and apparatus with neural network performing convolution S Lee US Patent App. 16/168,418, 2018 | 36* | 2018 |
| Accelerator in convolutional neural network and method for operating the same S Lee US Patent App. 15/662,225, 2017 | 35* | 2017 |
| Hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization CS Im, SH Lee, SW Lee, JD Lee, MK Jeong US Patent 8,688,885, 2014 | 35 | 2014 |
| Efficient identification of bad signatures in RSA-type batch signature S Lee, S Cho, J Choi, Y Cho IEICE Transactions on Fundamentals of Electronics, Communications and …, 2006 | 27 | 2006 |
| Apparatus and method of detecting errors in embedded software H Kim, K Yim, SW Lee, J Yoo, J Lee, Y Shin US Patent 8,589,889, 2013 | 24 | 2013 |
| System and method for dynamic task migration on multiprocessor system S Lee US Patent 8,832,174, 2014 | 22 | 2014 |
| Method of determining multimedia architectural pattern, and apparatus and method for transforming single-core based architecture to multi-core based architecture S Lee US Patent 9,021,430, 2015 | 17 | 2015 |
| Method and apparatus for migrating task in multi-processor system S Lee US Patent 8,171,267, 2012 | 17 | 2012 |
| Reconfigurable processor and operation method therefor S Lee US Patent 10,396,797, 2019 | 16 | 2019 |
| Computing system, method and computer-readable medium for managing a processing of tasks S Lee US Patent 8,799,913, 2014 | 15 | 2014 |
| Aquabolt-XL HBM2-PIM, LPDDR5-PIM with in-memory processing, and AXDIMM with acceleration buffer JH Kim, SH Kang, S Lee, H Kim, Y Ro, S Lee, D Wang, J Choi, J So, ... IEEE Micro 42 (3), 20-30, 2022 | 13 | 2022 |
| Method and apparatus for preventing stack overflow in embedded system S Lee US Patent 9,280,500, 2016 | 12 | 2016 |
Youngsam ShinPrincipal Engineer at Samsung Electronics (SAIT)Verified email at samsung.com
