| ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems GN Jyothi, K Sanapala, A Vijayalakshmi International Journal of Speech Technology 23 (2), 259-264, 2020 | 27 | 2020 |
| Ultra‐low‐voltage GDI‐based hybrid full adder design for area and energy‐efficient computing systems K Sanapala, R Sakthivel IET Circuits, Devices & Systems 13 (4), 465-470, 2019 | 26 | 2019 |
| Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications K Sanapala, SS Yeo The Journal of Supercomputing 74, 4613-4622, 2018 | 17 | 2018 |
| Analysis of GDI logic for minimum energy optimal supply voltage K Sanapala, R Sakthivel 2017 International conference on Microelectronic Devices, Circuits and …, 2017 | 9 | 2017 |
| A hadoop based framework integrating machine learning classifiers for anomaly detection in the internet of things IS Thaseen, V Mohanraj, S Ramachandran, K Sanapala, SS Yeo Electronics 10 (16), 1955, 2021 | 6 | 2021 |
| Low power realization of subthreshold digital logic circuits using body bias technique K Sanapala, R Sakthivel Indian Journal of Science and Technology 9 (5), 1-5, 2016 | 6 | 2016 |
| Two Novel Subthreshold Logic Families for Area and Ultra Low-Energy Efficient Applications: DTGDI & SBBGDI K Sanapala Gazi University Journal of Science 30 (4), 283-294, 2017 | 3 | 2017 |
| Design of 8 bit and 16 bit Reversible ALU for low power applications V Chandralekha, L Navya, N Syamala, K Sanapala 2020 IEEE 5th International Conference on Computing Communication and …, 2020 | 2 | 2020 |
| Design of ultralow voltage-hybrid full adder circuit using GLBB scheme for energy-efficient arithmetic applications K Sanapala, LR Shree, R Sakthivel Microelectronics, Electromagnetics and Telecommunications: Proceedings of …, 2018 | 2 | 2018 |
| Exploring CMOS logic families in sub-threshold region for ultra low power applications K Sanapala, K Madhuri, MS Sanju J. Electr Electron Eng 9 (1), 67-77, 2014 | 2 | 2014 |
| Low Power Modulo 2n+ 1 Multiplier Using Data Aware Adder Tree R Sakthivel, M Vanitha, K Sanapala, K Thirumalesh Procedia Computer Science 70, 355-361, 2015 | 1 | 2015 |
| Implementation of Sequence Detector using Optimized GDI Technique K Sanapala, VSV Prabhakar, D Pavan 2021 IEEE 4th International Conference on Computing, Power and Communication …, 2021 | | 2021 |
| Comparative Review of MAC Architectures P Dinesh, K Sanapala, GN Jyothi, R Sakthivel Soft Computing for Intelligent Systems: Proceedings of ICSCIS 2020, 27-33, 2021 | | 2021 |
| Near-zero computing using NCFET for IoT applications K Sanapala, SVV Satyanarayana, R Sakthivel International Journal of Intelligent Enterprise 8 (2-3), 288-295, 2021 | | 2021 |
| Performance Analysis of GDI based Arithmetic Circuits V Chandralekha, L Navya, K Sanapala, N Syamala 2020 IEEE 5th International Conference on Computing Communication and …, 2020 | | 2020 |
| Microelectronics, Electromagnetics and Telecommunications: Proceedings of ICMEET 2017 J Anguera, SC Satapathy, V Bhateja, KVN Sunitha Springer, 2018 | | 2018 |
| Design of Full Adder Using Subthreshold DTPT Logic K Sanapala Advances in Systems Science and Applications 16 (1), 85-94, 2016 | | 2016 |
Dr.Sakthivel RamachandranAssociate Professor, VIT University, Vellore, IndiaVerified email at vit.ac.in
