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Year
The Celerity open-source 511-core RISC-V tiered accelerator fabric: Fast architectures and design methodologies for fast chips
S Davidson, S Xie, C Torng, K Al-Hawai, A Rovinski, T Ajayi, L Vega, ...
IEEE Micro 38 (2), 30-41, 2018
852018
Rosetta: A realistic high-level synthesis benchmark suite for software programmable fpgas
Y Zhou, U Gupta, S Dai, R Zhao, N Srivastava, H Jin, J Featherston, ...
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
822018
Elasticflow: A complexity-effective approach for pipelining irregular loop nests
M Tan, G Liu, R Zhao, S Dai, Z Zhang
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 78-85, 2015
542015
A Parallel Bandit-Based Approach for Autotuning FPGA Compilation
C Xu, G Liu, R Zhao, S Yang, G Luo, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
432017
Architectural specialization for inter-iteration loop dependence patterns
S Srinath, B Ilbeyi, M Tan, G Liu, Z Zhang, C Batten
2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 583-595, 2014
382014
Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level Synthesis
S Dai, R Zhao, G Liu, S Srinath, U Gupta, C Batten, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
302017
Statistically certified approximate logic synthesis
G Liu, Z Zhang
2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 344-351, 2017
292017
Celerity: An Open Source RISC-V Tiered Accelerator Fabric
T Ajayi, K Al-Hawaj, A Amarnath, S Dai, S Davidson, P Gao, G Liu, A Lotfi, ...
Symp. on High Performance Chips (Hot Chips), 2017
292017
A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology Mapping
G Liu, Z Zhang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
192017
CASA: correlation-aware speculative adders
G Liu, Y Tao, M Tan, Z Zhang
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
172014
Improving high-level synthesis with decoupled data structure optimization
R Zhao, G Liu, S Srinath, C Batten, Z Zhang
2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 1-6, 2016
152016
Enabling adaptive loop pipelining in high-level synthesis
S Dai, G Liu, R Zhao, Z Zhang
2017 51st Asilomar Conference on Signals, Systems, and Computers, 131-135, 2017
122017
Architecture and synthesis for area-efficient pipelining of irregular loop nests
G Liu, M Tan, S Dai, R Zhao, Z Zhang
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
122017
A scalable approach to exact resource-constrained scheduling based on a joint SDC and SAT formulation
S Dai, G Liu, Z Zhang
Proceedings of the 2018 ACM/SIGDA International Symposium on Field …, 2018
112018
Experiences using the risc-v ecosystem to design an accelerator-centric soc in tsmc 16nm
TAKAH Aporva, ASDS Davidson, PGGLA Rao, ARNSC Torng, LVBVS Xie, ...
1st Workshop on Computer Architecture Research with RISC-V (CARRV 2017), 2017
112017
Evaluation of scattering in asymmetric quasi-ballistic DG-MOSFET
G Liu, G Du, T Lu, X Liu, P Zhang, X Zhang
Silicon Nanoelectronics Workshop (SNW), 2012 IEEE, 1-2, 2012
9*2012
Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set Specifications
G Liu, J Primmer, Z Zhang
Proceedings of the 56th Annual Design Automation Conference 2019, 122, 2019
82019
Simulation study of quasi-ballistic transport in asymmetric DG-MOSFET by directly solving Boltzmann transport equation
G Liu, G Du, T Lu, X Liu, P Zhang, X Zhang
IEEE transactions on nanotechnology 12 (2), 168-173, 2013
72013
A reconfigurable analog substrate for highly efficient maximum flow computation
G Liu, Z Zhang
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
52015
PIMap: A flexible framework for improving LUT-based technology mapping via parallelized iterative optimization
G Liu, Z Zhang
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 11 (4), 1-23, 2019
22019
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Articles 1–20