Edna Barros
Edna Barros
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The ArchC architecture description language and tools
R Azevedo, S Rigo, M Bartholomeu, G Araujo, C Araujo, E Barros
International Journal of Parallel Programming 33, 453-484, 2005
A method for partitioning UNITY language in hardware and software
E Barros, W Rosenstiel, X Xiong
Proc. EuroDAC 94, 220-225, 1994
Extreme value theory for estimating task execution time bounds: A careful look
G Lima, D Dias, E Barros
2016 28th Euromicro Conference on Real-Time Systems (ECRTS), 200-211, 2016
A Petri net model for hardware/software codesign
P Maciel, E Barros, W Rosenstiel
Design Automation for Embedded Systems 4, 243-310, 1999
An embedded automatic license plate recognition system using deep learning
DMF Izidio, APA Ferreira, HR Medeiros, ENS Barros
Design Automation for Embedded Systems 24 (1), 23-43, 2020
A method for hardware software partitioning
E Barros, W Rosenstiel
1992 Proceedings Computer Systems and Software Engineering, 580,581,582,583 …, 1992
A one-shot configurable-cache tuner for improved energy and performance
A Gordon-Ross, P Viana, F Vahid, W Najjar, E Barros
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
Hardware/software partitioning with UNITY
E Barros, W Rosenstiel, X Xiong
Proc. 2nd International Workshop on Hardware-Software Codesign, 1993
A constructive approach to hardware/software partitioning
L Silva, A Sampaio, E Barros
Formal Methods in System Design 24, 45-90, 2004
Towards provably correct hardware/software partitioning using OCCAM
E Barros, A Sampaio
Third International Workshop on Hardware/Software Codesign, 210-217, 1994
Hardware/Software partitioning using UNITY
ES Barros
(No Title), 1993
A normal form reduction strategy for hardware/software partitioning
L Silva, A Sampaio, E Barros
International Symposium of Formal Methods Europe, 624-643, 1997
Configurable cache subsetting for fast cache tuning
P Viana, A Gordon-Ross, E Keogh, E Barros, F Vahid
Proceedings of the 43rd annual Design Automation Conference, 695-700, 2006
Exploring memory hierarchy with ArchC
P Viana, E Barros, S Rigo, R Azevedo, G Araújo
Proceedings. 15th Symposium on Computer Architecture and High Performance …, 2003
An FPGA-based real-time occlusion robust stereo vision system using semi-global matching
LFS Cambuim, LA Oliveira Jr, ENS Barros, APA Ferreira
Journal of Real-Time Image Processing 17 (5), 1447-1468, 2020
A table-based method for single-pass cache optimization
P Viana, A Gordon-Ross, E Barros, F Vahid
Proceedings of the 18th ACM Great Lakes symposium on VLSI, 71-76, 2008
A safe, accurate intravenous infusion control system
E Barros, MVD des Santos
Ieee Micro 18 (5), 12-21, 1998
Hardware/Software co-design: projetando hardware e software concorrentemente
E Barros, S Cavalcante, ME de Lima, C Valderrama
IME-USP, 2000
Platform designer: An approach for modeling multiprocessor platforms based on SystemC
C Araujo, M Gomes, E Barros, S Rigo, R Azevedo, G Araujo
Design Automation for Embedded Systems 10, 253-283, 2005
A high performance full pipelined arquitecture of MLP neural networks in FPGA
APA Ferreira, ENS Barros
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
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