| Memory-reduced network stacking for edge-level CNN architecture with structured weight pruning S Moon, Y Byun, J Park, S Lee, Y Lee IEEE Journal on Emerging and Selected Topics in Circuits and Systems 9 (4 …, 2019 | 21 | 2019 |
| Layerwise buffer voltage scaling for energy-efficient convolutional neural network M Ha, Y Byun, S Moon, Y Lee, S Lee IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 13 | 2020 |
| FPGA-based sparsity-aware CNN accelerator for noise-resilient edge-level image recognition S Moon, H Lee, Y Byun, J Park, J Joe, S Hwang, S Lee, Y Lee 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 205-208, 2019 | 13 | 2019 |
| Selective deep convolutional neural network for low cost distorted image classification M Ha, Y Byun, J Kim, J Lee, Y Lee, S Lee Ieee Access 7, 133030-133042, 2019 | 13 | 2019 |
| Low-complexity dynamic channel scaling of noise-resilient CNN for intelligent edge devices Y Byun, M Ha, J Kim, S Lee, Y Lee 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 114-119, 2019 | 10 | 2019 |
| Multi-level weight indexing scheme for memory-reduced convolutional neural network J Park, S Moon, Y Byun, S Lee, Y Lee 2019 IEEE International Conference on Artificial Intelligence Circuits and …, 2019 | 4 | 2019 |
| Fixed-point quantization of 3d convolutional neural networks for energy-efficient action recognition H Lee, Y Byun, S Hwang, S Lee, Y Lee 2018 International SoC Design Conference (ISOCC), 129-130, 2018 | 3 | 2018 |
| Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers JG Min, D Kam, Y Byun, G Park, Y Lee 2023 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2023 | 1 | 2023 |
| Approach to improve the performance using bit-level sparsity in neural networks Y Kang, E Kwon, S Lee, Y Byun, Y Lee, S Kang 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021 | 1 | 2021 |
| Neural processing device and operation method thereof YJ Lee, S Lee, M Ha, Y Byun US Patent 11,748,612, 2023 | | 2023 |
| Sparsity-Aware Memory Interface Architecture using Stacked XORNet Compression for Accelerating Pruned-DNN Models Y Byun, S Moon, B Park, SJ Kwon, D Lee, G Park, E Yoo, JG Min, Y Lee Proceedings of Machine Learning and Systems 5, 2023 | | 2023 |
| CHAMP: Channel Merging Process for Cost-Efficient Highly-Pruned CNN Acceleration H Kwon, Y Byun, S Kang, Y Lee IEEE Transactions on Circuits and Systems I: Regular Papers 69 (8), 3308-3319, 2022 | | 2022 |
| Rapid Design Space Exploration of Near-Optimal Memory-Reduced DCNN Architecture Using Multiple Model Compression Techniques Y Byun, Y Lee 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2021 | | 2021 |
