Peter Beerel

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Souvik KunduResearch Scientist AI/ML, Intel LabsVerified email at intel.com
Massoud PedramCharles Lee Powell Professor of Electrical Engineering & Computer Science, Univ of SouthernVerified email at usc.edu
Keith ChuggProfessor of Electrical Engineering, USCVerified email at usc.edu
Gourav DattaResearch Assistant, University of Southern CaliforniaVerified email at usc.edu
Ken StevensProfessor of electrical and computer engineering, university of utahVerified email at ece.utah.edu
Chris MyersUniversity of UtahVerified email at ece.utah.edu
Ney Laert Vilar CalazansProfessor at the School of Technology, PUCRSVerified email at pucrs.br
Matheus Trevisan MoreiraMetaVerified email at meta.com
Ramy N. TadrosQualcommVerified email at qti.qualcomm.com
Ran GinosarProfessor of EE & CS, TechnionVerified email at ee.technion.ac.il
Sourya DeyGaloisVerified email at galois.com
Mike DaviesDirector, Neuromorphic Computing Lab, IntelVerified email at intel.com
Huimei ChengUniversity of Southern CaliforniaVerified email at usc.edu
Arash SaifhashemiResearch Scientist, Intel LabsVerified email at intel.com
Jerry R. BurchSynopsys, Inc.Verified email at fun-journey.com
Steven NowickProfessor of Computer Science, Columbia UniversityVerified email at cs.columbia.edu
Akhilesh JaiswalResearch Assistant Professor, University of Southern California - Information Sciences InstituteVerified email at isi.edu
Mehrdad Najibi,Senior Member of Technical Staff, Cadence Design SystemsVerified email at usc.edu
Phunsak ThiennviboonDepartment of Electrical Engineering, Kasetsart UniversityVerified email at ku.th
Yang ZhangUniversity of Southern CaliforniaVerified email at usc.edu

Peter Beerel

Professor of Electrical and Computer Engineering, USC

Verified email at usc.edu - Homepage

Machine Learning Hardware Security Superconducting Electronics CAD/VLSI


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Optimization of cell subtypes in a hierarchical design flow F Eaton, P Beerel US Patent 6,854,096, 2005	284	2005
A designer's guide to asynchronous VLSI PA Beerel, RO Ozdag, M Ferretti Cambridge University Press, 2010	253	2010
Automatic gate-level synthesis of speed-independent circuits PA Beerel, THY Meng ICCAD, 581-586, 1992	189	1992
Speculative completion for the design of high-performance asynchronous dynamic adders SM Nowick, KY Yun, PA Beerel, AE Dooply Proceedings Third International Symposium on Advanced Research in …, 1997	159	1997
The design and verification of a high-performance low-control-overhead asynchronous differential equation solver KY Yun, PA Beerel, V Vakilotojar, AE Dooply, J Arceo IEEE transactions on very large scale integration (VLSI) systems 6 (4), 643-655, 1998	152	1998
High performance asynchronous ASIC back-end design flow using single-track full-buffer standard cells M Ferretti, RO Ozdag, PA Beerel 10th International Symposium on Asynchronous Circuits and Systems, 2004 …, 2004	143	2004
High-performance asynchronous pipeline circuits KY Yun, PA Beerel, J Arceo Proceedings Second International Symposium on Advanced Research in …, 1996	131	1996
Slack matching asynchronous designs PA Beerel, A Lines, M Davies, NH Kim 12th IEEE International Symposium on Asynchronous Circuits and Systems …, 2006	117	2006
RAPPID: An asynchronous instruction length decoder S Rotem, K Stevens, R Ginosar, P Beerel, C Myers, K Yun, R Kol, C Dike, ... Proceedings. Fifth International Symposium on Advanced Research in …, 1999	114	1999
Proteus: An ASIC flow for GHz asynchronous designs PA Beerel, GD Dimou, AM Lines IEEE Design & Test of Computers 28 (5), 36-51, 2011	108	2011
An asynchronous instruction length decoder KS Stevens, S Rotem, R Ginosar, P Beerel, CJ Myers, KY Yun, R Koi, ... IEEE Journal of solid-state circuits 36 (2), 217-228, 2001	107	2001
High-speed QDI asynchronous pipelines RO Ozdag, PA Beerel Proceedings Eighth International Symposium on Asynchronous Circuits and …, 2002	105	2002
Single-track asynchronous pipeline templates using 1-of-N encoding M Ferretti, PA Beerel Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002	98	2002
Safe BDD minimization using don't cares Y Hong, PA Beerel, JR Burch, KL McMillan Proceedings of the 34th annual Design Automation Conference, 208-213, 1997	91	1997
Semi-modularity and testability of speed-independent circuits PA Beerel, THY Meng Integration 13 (3), 301-322, 1992	82	1992
Symbolic techniques for performance analysis of timed systems based on average time separation of events A Xie, PA Beerel Proceedings Third International Symposium on Advanced Research in …, 1997	74	1997
Blade--a timing violation resilient asynchronous template D Hand, MT Moreira, HH Huang, D Chen, F Butzke, Z Li, M Gibiluka, ... 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015	71	2015
Bounding average time separations of events in stochastic timed Petri nets with choice A Xie, S Kim, PA Beerel Proceedings. Fifth International Symposium on Advanced Research in …, 1999	70	1999
Pipeline optimization for asynchronous circuits: Complexity analysis and an efficient optimal algorithm S Kim, PA Beerel IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006	64	2006
Efficient state classification of finite state Markov chains A Xie, PA Beerel Proceedings of the 35th annual Design Automation Conference, 605-610, 1998	63	1998

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