| A comprehensive methodology to optimize FPGA designs via the roofline model M Siracusa, E Del Sozzo, M Rabozzi, L Di Tucci, S Williams, D Sciuto, ... IEEE Transactions on Computers 71 (8), 1903-1915, 2021 | 26 | 2021 |
| The performance and energy efficiency potential of FPGAs in scientific computing T Nguyen, S Williams, M Siracusa, C MacLean, D Doerfler, NJ Wright 2020 IEEE/ACM Performance Modeling, Benchmarking and Simulation of High …, 2020 | 26 | 2020 |
| FPGA‐based HPC accelerators: An evaluation on performance and energy efficiency T Nguyen, C MacLean, M Siracusa, D Doerfler, NJ Wright, S Williams Concurrency and Computation: Practice and Experience 34 (20), e6570, 2022 | 22 | 2022 |
| A cad-based methodology to optimize hls code via the roofline model M Siracusa, L Di Tucci, M Rabozzi, S Williams, ED Sozzo, ... Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 22 | 2020 |
| Scaling up HBM efficiency of top-K spmv for approximate embedding similarity on fpgas A Parravicini, LG Cellamare, M Siracusa, MD Santambrogio 2021 58th ACM/IEEE Design Automation Conference (DAC), 799-804, 2021 | 11 | 2021 |
| Solving large top-K graph eigenproblems with a memory and compute-optimized FPGA design F Sgherzi, A Parravicini, M Siracusa, MD Santambrogio 2021 IEEE 29th Annual International Symposium on Field-Programmable Custom …, 2021 | 7 | 2021 |
| Tensor optimization for high-level synthesis design flows M Siracusa, F Ferrandi IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2020 | 7 | 2020 |
| Automated design space exploration and roofline analysis for FPGA-based HLS applications M Siracusa, M Rabozzi, E Del Sozzo, MD Santambrogio, L Di Tucci 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom …, 2019 | 7 | 2019 |
| Experiences porting the su3_bench microbenchmark to the intel arria 10 and xilinx alveo u280 fpgas D Doerfler, F Fatollahi-Fard, C MacLean, T Nguyen, S Williams, N Wright, ... International Workshop on OpenCL, 1-9, 2021 | 3 | 2021 |
| Method of realizing a hardware device for executing operations defined by a high-level software code M Siracusa, M Rabozzi, L Di Tucci, MD Santambrogio, F Pizzato US Patent 11,790,140, 2023 | | 2023 |
| A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors M Siracusa, V Soria-Pardos, F Sgherzi, J Randall, D J. Joseph, ... Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | | 2023 |
| SpChar: Characterizing the Sparse Puzzle via Decision Trees F Sgherzi, M Siracusa, I Fernandez, A Armejach, M Moretó arXiv preprint arXiv:2304.06944, 2023 | | 2023 |
| METODO PER REALIZZARE UN DISPOSITIVO HARDWARE PER ESEGUIRE OPERAZIONI DEFINITE DA UN CODICE SOFTWARE DI ALTO LIVELLO M Siracusa, M Rabozzi, L Di Tucci, M Santambrogio, F Pizzato | | 2019 |
| A toolchain to optimize HLS applications via the Roofline model M SIRACUSA Politecnico di Milano, 2019 | | 2019 |
