| Memory consistency and event ordering in scalable shared-memory multiprocessors K Gharachorloo, D Lenoski, J Laudon, P Gibbons, A Gupta, J Hennessy ACM SIGARCH Computer Architecture News 18 (2SI), 15-26, 1990 | 1823 | 1990 |
| Shared memory consistency models: A tutorial SV Adve, K Gharachorloo computer 29 (12), 66-76, 1996 | 1624 | 1996 |
| The stanford dash multiprocessor D Lenoski, J Laudon, K Gharachorloo, WD Weber, A Gupta, J Hennessy, ... Computer 25 (3), 63-79, 1992 | 1471 | 1992 |
| The stanford flash multiprocessor J Kuskin, D Ofelt, M Heinrich, J Heinlein, R Simoni, K Gharachorloo, ... Proceedings of the 21ST annual international symposium on Computer …, 1994 | 1091 | 1994 |
| The directory-based cache coherence protocol for the DASH multiprocessor D Lenoski, J Laudon, K Gharachorloo, A Gupta, J Hennessy ACM SIGARCH Computer Architecture News 18 (2SI), 148-159, 1990 | 995 | 1990 |
| Piranha: A scalable architecture based on single-chip multiprocessing LA Barroso, K Gharachorloo, R McNamara, A Nowatzyk, S Qadeer, ... ACM SIGARCH Computer Architecture News 28 (2), 282-293, 2000 | 790 | 2000 |
| Memory system characterization of commercial workloads LA Barroso, K Gharachorloo, E Bugnion Proceedings of the 25th annual international symposium on Computer …, 1998 | 564 | 1998 |
| Shasta: A low overhead, software-only approach for supporting fine-grain shared memory DJ Scales, K Gharachorloo, CA Thekkath Proceedings of the seventh international conference on Architectural support …, 1996 | 476 | 1996 |
| Method for sharing variable-grained memory of workstations by sending particular block including line and size of the block to exchange shared data structures DJ Scales, K Gharachorloo US Patent 5,933,598, 1999 | 388 | 1999 |
| Performance evaluation of memory consistency models for shared-memory multiprocessors K Gharachorloo, A Gupta, J Hennessy ACM SIGPLAN Notices 26 (4), 245-257, 1991 | 361 | 1991 |
| Two techniques to enhance the performance of memory consistency models K Gharachorloo, A Gupta, JL Hennessy Computer Systems Laboratory, Stanford University, 1991 | 351 | 1991 |
| Tolerating latency through software-controlled data prefetching TC Mowry stanford university, 1994 | 345 | 1994 |
| An analysis of database workload performance on simultaneous multithreaded processors JL Lo, LA Barroso, SJ Eggers, K Gharachorloo, HM Levy, SS Parekh ACM SIGARCH Computer Architecture News 26 (3), 39-50, 1998 | 316 | 1998 |
| Comparative evaluation of latency reducing and tolerating techniques A Gupta, J Hennessy, K Gharachorloo, T Mowry, WD Weber Proceedings of the 18th Annual International Symposium on Computer …, 1991 | 293 | 1991 |
| Better verification through symmetry CN Ip, DL Dill Computer Hardware Description Languages and their Applications, 97-111, 1993 | 289 | 1993 |
| Scalable architecture based on single-chip multiprocessing LA Barroso, K Gharachorloo, A Nowatzyk US Patent 6,668,308, 2003 | 264 | 2003 |
| Performance of database workloads on shared-memory systems with out-of-order processors P Ranganathan, K Gharachorloo, SV Adve, LA Barroso Proceedings of the eighth international conference on Architectural support …, 1998 | 242 | 1998 |
| Multiprocessors should support simple memory consistency models MD Hill Computer 31 (8), 28-34, 1998 | 219 | 1998 |
| Memory consistency models for shared-memory multiprocessors K Gharachorloo Stanford University, 1996 | 215 | 1996 |
| The performance impact of flexibility in the Stanford FLASH multiprocessor M Heinrich, J Kuskin, D Ofelt, J Heinlein, J Baxter, JP Singh, R Simoni, ... Proceedings of the sixth international conference on Architectural support …, 1994 | 193 | 1994 |
