| Impact of analog non-idealities on the design space of 6T-SRAM current-domain dot-product operators for in-memory computing A Kneip, D Bol IEEE Transactions on Circuits and Systems I: Regular Papers 68 (5), 1931-1944, 2021 | 20 | 2021 |
| SleepRider: A 5.5 μW/MHz cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, biomedical AFE and fully-integrated power, clock and back-bias management R Dekimpe, M Schramme, M Lefebvre, A Kneip, R Saeidi, M Xhonneux, ... 2021 Symposium on VLSI Circuits, 1-2, 2021 | 10 | 2021 |
| A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization A Kneip, M Lefebvre, J Verecken, D Bol ESSCIRC 2022-IEEE 48th European Solid State Circuits Conference (ESSCIRC …, 2022 | 5 | 2022 |
| IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm CIM-SRAM With Multi-Bit Analog … A Kneip, M Lefebvre, J Verecken, D Bol IEEE Journal of Solid-State Circuits, 2023 | 3 | 2023 |
| A 7T-NDR dual-supply 28-nm FD-SOI ultra-low power SRAM with 0.23-nW/kB sleep retention and 0.8 pJ/32b access at 64 MHz with forward back bias A Kneip, D Bol IEEE Transactions on Circuits and Systems I: Regular Papers 70 (3), 1311-1323, 2023 | 2 | 2023 |
| Bridging the hardware-software co-design gap in analog compute-in-memory accelerators towards edge CNN classification A Kneip UCL-Université Catholique de Louvain, 2024 | | 2024 |
| Design and optimization of an ultra-low power SRAM macro for the Internet-of-Things A Kneip, D Bol | | |
