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Ioannis Tsiokanos
Ioannis Tsiokanos
Verified email at qub.ac.uk
Title
Cited by
Cited by
Year
Low-power variation-aware cores based on dynamic data-dependent bitwidth truncation
I Tsiokanos, L Mukhanov, G Karakonstantis
2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 698-703, 2019
172019
Accurate estimation of dynamic timing slacks using event-driven simulation
D Garyfallou, I Tsiokanos, N Evmorfopoulos, G Stamoulis, ...
2020 21st International Symposium on Quality Electronic Design (ISQED), 225-230, 2020
92020
Variation-aware pipelined cores through path shaping and dynamic cycle adjustment: Case study on a floating-point unit
I Tsiokanos, L Mukhanov, DS Nikolopoulos, G Karakonstantis
Proceedings of the International Symposium on Low Power Electronics and …, 2018
92018
Significance-driven data truncation for preventing timing failures
I Tsiokanos, L Mukhanov, DS Nikolopoulos, G Karakonstantis
IEEE Transactions on Device and Materials Reliability 19 (1), 25-36, 2019
82019
DEFCON: generating and detecting failure-prone instruction sequences via stochastic search
I Tsiokanos, L Mukhanov, G Georgakoudis, DS Nikolopoulos, ...
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2020
62020
Minimization of timing failures in pipelined designs via path shaping and operand truncation
I Tsiokanos, L Mukhanov, DS Nikolopoulos, G Karakonstantis
2018 IEEE 24th International Symposium on On-Line Testing And Robust System …, 2018
52018
DTA-PUF: Dynamic Timing-aware Physical Unclonable Function for Resource-constrained Devices
I Tsiokanos, J Miskelly, C Gu, M O’neill, G Karakonstantis
ACM Journal on Emerging Technologies in Computing Systems (JETC) 17 (3), 1-24, 2021
42021
Exhero: Execution history-aware error-rate estimation in pipelined designs
I Tsiokanos, G Karakonstantis
IEEE Micro 41 (1), 61-68, 2020
32020
Instruction-aware Learning-based Timing Error Models through Significance-driven Approximations
S Tompazi, I Tsiokanos, J Martinez-del-Rincon, G Karakonstantis, ...
IEEE International Conference on Computer Design, 2022
2022
ARETE: Accurate Error Assessment via Machine Learning-Guided Dynamic-Timing Analysis
I Tsiokanos, S Tompazi, G Georgakoudis, L Mukhanov, G Karakonstantis
IEEE Transactions on Computers, 2022
2022
Hardware Level Approximations
I Tsiokanos, G Papadimitriou, D Gizopoulos, G Karakonstantis
Approximate Computing Techniques, 43-79, 2022
2022
Estimating Code Vulnerability to Timing Errors via Microarchitecture-Aware Machine Learning
S Tompazi, I Tsiokanos, JM Del Rincon, G Karakonstantis
IEEE Design & Test, 2021
2021
Boosting Microprocessor Efficiency: Circuit-and Workload-Aware Assessment of Timing Errors
I Tsiokanos, G Papadimitriou, D Gizopoulos, G Karakonstantis
2021 IEEE International Symposium on Workload Characterization (IISWC), 125-137, 2021
2021
Cross-layer instruction-aware timing error mitigation & evaluation for energy-efficient dependable architectures
I Tsiokanos
Queen's University Belfast, 2021
2021
SPECIAL SECTION ON IOLTS
D Gizopoulos, D Alexandrescu, M Nicolaidis, LB Faber, ML Flottes, ...
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