| Design of CNTFET-based ternary ALU using 2: 1 multiplexer based approach S Gadgil, C Vudadha IEEE Transactions on Nanotechnology 19, 661-671, 2020 | 26 | 2020 |
| A novel low power ternary multiplier design using cnfets H Sirugudi, S Gadgil, C Vudadha 2020 33rd International Conference on VLSI Design and 2020 19th …, 2020 | 11 | 2020 |
| Design of area optimised, energy efficient quaternary circuits using CNTFETs P Patel, N Doddapaneni, S Gadgil, C Vudadha 2019 Ieee International Symposium On Smart Electronic Systems (Ises …, 2019 | 6 | 2019 |
| Novel design methodologies for CNFET-based ternary sequential logic circuits S Gadgil, C Vudadha IEEE Transactions on Nanotechnology 21, 289-298, 2022 | 4 | 2022 |
| Design of CNFET-based low-power ternary sequential logic circuits S Gadgil, C Vudadha 2021 IEEE 21st International Conference on Nanotechnology (NANO), 169-172, 2021 | 4 | 2021 |
| Power efficient designs of CNTFET-based ternary SRAM S Gadgil, C Sandesh, Goli Naga: Vudadha Microelectronics Journal, 2023 | 3 | 2023 |
| Design and Implementation of a CNTFET-Based Ternary Logic Processor S Gadgil, GN Sandesh Authorea Preprints, 2023 | 1 | 2023 |
| Design of CNTFET-based Ternary Logic circuits using Low power Encoder T Siddharth, S Gadgil, C Vudadha 2022 IEEE International Symposium on Smart Electronic Systems (iSES), 142-147, 2022 | 1 | 2022 |
| COMPACT IMPLEMENTATION OF DSSS WAVEFORM USING XILINX ZYNQ SOC AND AD9361 TRANSCEIVER S Gadgil, A Pawar, CD Naidu, M Haritha | | |
Chetan Kumar VudadhaBITS-Pilani, Hyderabad CampusVerified email at hyderabad.bits-pilani.ac.in
