| An integrated system-on-chip test framework E Larsson, Z Peng Design, Automation, and Test in Europe, 439-454, 2008 | 111 | 2008 |
| An integrated framework for the design and optimization of SOC test solutions E Larsson, Z Peng, K Chakrabarty SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, 21-36, 2002 | 111 | 2002 |
| Efficient test solutions for core-based designs E Larsson Introduction to Advanced System-on-Chip Test Design and Optimization, 215-251, 2005 | 76 | 2005 |
| Test scheduling and scan-chain division under power constraint E Larsson, Z Peng Proceedings 10th Asian Test Symposium, 259-264, 2001 | 67 | 2001 |
| Design automation for IEEE P1687 FG Zadegan, U Ingelsson, G Carlsson, E Larsson 2011 Design, Automation & Test in Europe, 1-6, 2011 | 66 | 2011 |
| Cycle-accurate test power modeling and its application to SoC test scheduling S Samii, E Larsson, K Chakrabarty, Z Peng 2006 IEEE International Test Conference, 1-10, 2006 | 48 | 2006 |
| System-on-chip test scheduling with reconfigurable core wrappers E Larsson, H Fujiwara IEEE transactions on very large scale integration (VLSI) systems 14 (3), 305-309, 2006 | 48 | 2006 |
| Introduction to advanced system-on-chip test design and optimization E Larsson Springer Science & Business Media, 2005 | 48 | 2005 |
| A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling. E Larsson, Z Peng ITC, 1135-1144, 2003 | 47 | 2003 |
| Access time analysis for IEEE P1687 FG Zadegan, U Ingelsson, G Carlsson, E Larsson IEEE Transactions on Computers 61 (10), 1459-1472, 2011 | 43 | 2011 |
| Multiple-constraint driven system-on-chip test time optimization J Pouget, E Larsson, Z Peng Journal of electronic testing 21 (6), 599-611, 2005 | 43 | 2005 |
| A suite of IEEE 1687 benchmark networks A Tšertov, A Jutman, S Devadze, MS Reorda, E Larsson, FG Zadegan, ... 2016 IEEE International Test Conference (ITC), 1-10, 2016 | 42 | 2016 |
| Test scheduling for modular SOCs in an abort-on-fail environment U Ingelsson, SK Goel, E Larsson, EJ Marinissen European Test Symposium (ETS'05), 8-13, 2005 | 42 | 2005 |
| On minimization of peak power for scan circuit during test JT Tudu, E Larsson, V Singh, VD Agrawal 2009 14th IEEE European Test Symposium, 25-30, 2009 | 38 | 2009 |
| Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns A Larsson, E Larsson, K Chakrabarty, P Eles, Z Peng 2008 Design, Automation and Test in Europe, 188-193, 2008 | 38 | 2008 |
| SOC test time minimization under multiple constraints J Pouget, E Larsson, Z Peng 2003 Test Symposium, 312-312, 2003 | 38 | 2003 |
| Power constrained preemptive TAM scheduling E Larsson, H Fujiwara Proceedings The Seventh IEEE European Test Workshop, 119-126, 2002 | 37 | 2002 |
| Defect-aware SOC test scheduling E Larsson, J Pouget, Z Peng 22nd IEEE VLSI Test Symposium, 2004. Proceedings., 359-364, 2004 | 36 | 2004 |
| Test scheduling in an IEEE P1687 environment with resource and power constraints FG Zadegan, U Ingelsson, G Asani, G Carlsson, E Larsson 2011 Asian Test Symposium, 525-531, 2011 | 34 | 2011 |
| Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors P Subramanyan, V Singh, KK Saluja, E Larsson 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010 …, 2010 | 34 | 2010 |
Artur JutmanTalTechVerified email at pld.ttu.ee
