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Tuo-Hung (Alex) Hou
Tuo-Hung (Alex) Hou
Institute of Electronics; National Yang Ming Chiao Tung University
Verified email at nycu.edu.tw
Title
Cited by
Cited by
Year
Origin of the threshold voltage instability in SiO2/HfO2 dual layer gate dielectrics
A Kerber, E Cartier, L Pantisano, R Degraeve, T Kauerauf, Y Kim, A Hou, ...
IEEE Electron Device Letters 24 (2), 87-89, 2003
4202003
Recommended methods to study resistive switching devices
M Lanza, HSP Wong, E Pop, D Ielmini, D Strukov, BC Regan, L Larcher, ...
Advanced Electronic Materials 5 (1), 1800143, 2019
4142019
Electrode dependence of filament formation in HfO2 resistive-switching memory
KL Lin, TH Hou, J Shieh, JH Lin, CT Chou, YJ Lee
Journal of Applied Physics 109 (8), 084104, 2011
3182011
Bipolar Nonlinear Selector for 1S1R Crossbar Array Applications
JJ Huang, YM Tseng, CW Hsu, TH Hou
IEEE Electron Device Letters 32 (10), 1427-1429, 2011
1992011
Transition of stable rectification to resistive-switching in oxide diode
JJ Huang, CW Kuo, WC Chang, TH Hou
Applied Physics Letters 96 (26), 262901, 2010
1822010
Mitigating effects of non-ideal synaptic device characteristics for on-chip learning
PY Chen, B Lin, IT Wang, TH Hou, J Ye, S Vrudhula, J Seo, Y Cao, S Yu
2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 194-199, 2015
1712015
Optically initialized robust valley-polarized holes in monolayer WSe2
WT Hsu, YL Chen, CH Chen, PS Liu, TH Hou, LJ Li, WH Chang
Nature communications 6 (1), 1-8, 2015
1672015
Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application
CH Chen, TL Lee, TH Hou, CL Chen, CC Chen, JW Hsu, KL Cheng, ...
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 56-57, 2004
1662004
Characterization and modeling of nonfilamentary Ta/TaOx/TiO2/Ti analog synaptic device
YF Wang, YC Lin, I Wang, TP Lin, TH Hou
Scientific reports 5 (1), 1-9, 2015
1562015
Multi-level control of conductive nano-filament evolution in HfO 2 ReRAM by pulse-train operations
HS PhilipáWong
Nanoscale 6 (11), 5698-5702, 2014
1492014
3D Ta/TaOx/TiO2/Ti synaptic array and linearity tuning of weight update for hardware neural network applications
IT Wang, CC Chang, LW Chiu, T Chou, TH Hou
Nanotechnology 27 (36), 365204, 2016
1332016
One selector-one resistor (1S1R) crossbar array for high-density flexible memory applications
JJ Huang, YM Tseng, WC Luo, CW Hsu, TH Hou
2011 international electron devices meeting, 31.7. 1-31.7. 4, 2011
1322011
Self-rectifying bipolar TaOx/TiO2 RRAM with superior endurance over 1012 cycles for 3D high-density storage-class memory
CW Hsu, IT Wang, CL Lo, MC Chiang, WY Jang, CH Lin, TH Hou
2013 Symposium on VLSI Technology, T166-T167, 2013
1212013
High-k gate stacks for planar, scaled CMOS integrated circuits
HR Huff, A Hou, C Lim, Y Kim, J Barnett, G Bersuker, GA Brown, ...
Microelectronic Engineering 69 (2-4), 152-167, 2003
1182003
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
L Gao, IT Wang, PY Chen, S Vrudhula, J Seo, Y Cao, TH Hou, S Yu
Nanotechnology 26 (45), 455204, 2015
1082015
Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
TH Hou, MF Wang, CC Chen, CW Yang, LG Yao, SC Chen
US Patent 6,890,811, 2005
1062005
3D synaptic architecture with ultralow sub-10 fJ energy per spike for neuromorphic computation
IT Wang, YC Lin, YF Wang, CW Hsu, TH Hou
2014 IEEE International Electron Devices Meeting, 28.5. 1-28.5. 4, 2014
992014
Mitigating asymmetric nonlinear weight update effects in hardware neural network based on analog resistive synapse
CC Chang, PC Chen, T Chou, IT Wang, B Hudec, CC Chang, CM Tsai, ...
IEEE Journal on Emerging and Selected Topics in Circuits and Systems 8 (1 …, 2017
952017
Conventional n-Channel MOSFET Devices Using Single Layer HfO~ 2 and ZrO~ 2 as High-k Gate Dielectrics with Polysilicon Gate Electrode
Y Kim, G Gebara, M Freiler, J Barnett, D Riley, J Chen, K Torres, JE Lim, ...
International Electron Devices Meeting, 455-458, 2001
922001
Design optimization of metal nanocrystal memory—Part I: Nanocrystal array engineering
TH Hou, C Lee, V Narayanan, U Ganguly, EC Kan
IEEE transactions on electron devices 53 (12), 3095-3102, 2006
852006
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