Dongyun Kam
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Grow: A row-stationary sparse-dense gemm accelerator for memory-efficient graph convolutional neural networks
R Hwang, M Kang, J Lee, D Kam, Y Lee, M Rhu
2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023
Massive MIMO systems with low-resolution ADCs: Baseband energy consumption vs. symbol detection performance
S Moon, IS Kim, D Kam, DW Jee, J Choi, Y Lee
IEEE Access 7, 6650-6660, 2019
Ultra-low-latency parallel SC polar decoding architecture for 5G wireless communications
D Kam, Y Lee
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019
A 1.1μs 1.56Gb/s/mm2 Cost-Efficient Large-List SCL Polar Decoder Using Fully-Reusable LLR Buffers in 28nm CMOS Technology
D Kam, BY Kong, Y Lee
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2022
Ultralow-latency successive cancellation polar decoding architecture using tree-level parallelism
D Kam, H Yoo, Y Lee
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (6 …, 2021
High-throughput and low-latency digital baseband architecture for energy-efficient wireless VR systems
S Hwang, S Moon, D Kam, IY Oh, Y Lee
Electronics 8 (7), 815, 2019
Low-latency SCL polar decoder architecture using overlapped pruning operations
D Kam, BY Kong, Y Lee
IEEE Transactions on Circuits and Systems I: Regular Papers 70 (3), 1417-1427, 2023
Low-latency polar decoder using overlapped SCL processing
D Kam, BY Kong, Y Lee
ICASSP 2021-2021 IEEE International Conference on Acoustics, Speech and …, 2021
Ultra-low-latency LDPC decoding architecture using reweighted offset min-sum algorithm
S Yun, D Kam, J Choe, BY Kong, Y Lee
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
Simplified ordered statistic decoding for short-length linear block codes
C Kim, D Kam, S Kim, G Park, Y Lee
IEEE Communications Letters 26 (8), 1720-1724, 2022
Design and evaluation frameworks for advanced risc-based ternary processor
D Kam, JG Min, J Yoon, S Kim, S Kang, Y Lee
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022
FPGA-based ordered statistic decoding architecture for B5G/6G URLLC IIoT networks
C Kim, D Rim, J Choe, D Kam, G Park, S Kim, Y Lee
2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1-3, 2021
2.8 A 21.9 ns 15.7 Gbps/mm² (128, 15) BOSS FEC Decoder for 5G/6G URLLC Applications
D Kam, S Yun, J Choe, Z Zhang, N Lee, Y Lee
2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 50-52, 2024
Energy-Efficient RISC-V-Based Vector Processor for Cache-Aware Structurally-Pruned Transformers
JG Min, D Kam, Y Byun, G Park, Y Lee
2023 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2023
Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithm
S Hong, D Kam, S Yun, J Choe, N Lee, Y Lee
IEEE Transactions on Circuits and Systems I: Regular Papers 69 (4), 1774-1787, 2021
Hard-Decision SCL Polar Decoder With Weighted Pruning Operation for Storage Applications
D Park, D Kam, S Yun, J Choe, Y Lee
IEEE Transactions on Circuits and Systems II: Express Briefs, 2024
저지연 SC 폴라 복호화기의 성능 분석 및 최적화
감동윤, 이영주
한국통신학회 학술대회논문집, 334-335, 2019
M Geiselhart, M Ebada, A Elkelesh, J Clausius, S ten Brink, L Zhang, ...
EM Side-Channel Countermeasure for Switched-Capacitor DC–DC Converters Based on Amplitude Modulation................................................... R. Jevtic, M. Ylitolva …
D Kam, H Yoo, Y Lee, Z Chen
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