| Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools MLL Sartori, RN Wuerdig, MT Moreira, NLV Calazans 2019 IEEE International Symposium on Asynchronous Circuits and Systems …, 2019 | 11 | 2019 |
| Leveraging qdi robustness to simplify the design of iot circuits MLL Sartori, RN Wuerdig, MT Moreira, S Bampi, NLV Calazans 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 6 | 2020 |
| Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations RN Wuerdig, MLL Sartori, NLV Calazans 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 137-140, 2019 | 3 | 2019 |
| AV1 Residual Syntax Elements Assessment and Efficient VLSI Architecture JS Gomes, RN Wuerdig, FLL Ramos, S Bampi 2023 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems …, 2023 | 1 | 2023 |
| Mitigating Asynchronous QDI Drawbacks on MAC Operators with Approximate Multipliers RN Wuerdig, MLL Sartori, BA Abreu, S Bampi, NLV Calazans 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1269-1273, 2022 | 1 | 2022 |
| Enhancing Side Channel Attack-Resistance of the STTL Combining Multi-Vt Transistors with Capacitance and Current Paths Counterbalancing VG LIMA, GP PAIM, RN WUERDIG, LMG ROCHA, L ROSA JUNIOR, ... Journal of Integrated Circuits and Systems 15 (1), 2020 | 1 | 2020 |
| Comparative Implementation of PicoSoC System-on-Chip in X-Fab 180 nm CMOS Technology R Wuerdig, LH Brendler, C Diniz, R Reis, S Bampi Journal of Integrated Circuits and Systems 19 (1), 1-7, 2024 | | 2024 |
| RISC-V SoC Physical Implementation in 180 nm CMOS with a Quark Core Based on FemtoRV32 FF Nascimento, RN Wuerdig, AF Ponchet, B Sanches, DS Loubach, ... 2023 IEEE Seventh Ecuador Technical Chapters Meeting (ECTM), 1-6, 2023 | | 2023 |
| LEX-A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization RN Wuerdig, VH Maciel, R Reis, S Bampi 2023 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 1-6, 2023 | | 2023 |
| Designing a 9.3 μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC RN Wuerdig, B Canal, TR Balen, S Bampi 2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems …, 2022 | | 2022 |
| Low power design of CMOS time to digital converters RN Wuerdig | | 2022 |
| Evaluating Cell Library Sizing Methodologies for Ultra-Low Power Near-Threshold Operation in Bulk CMOS RN Wuerdig, VG Lima, F Baumgratz, R Soares, S Bampi 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 1-4, 2020 | | 2020 |
| Logical and Physical Synthesis of an HF-RISCV Core for X-Fab 180 nm Technology RLAR Rodrigo N. Wuerdig, Lúcio P. Franco, Rodrigo F. Scroferneker, Carolina ... Revista Jr de Iniciação Científica em Ciências Exatas e Engenharia - ISSN …, 2020 | | 2020 |
| Desenvolvimento de Bibliotecas de Células Digitais CMOS de 28nm para Computação de Ultrabaixo Consumo (ULP-NTC) RN Wuerdig | | 2019 |
| A 1 GHz 64 b Serial Peripheral Interface for 40 nm Bulk CMOS Technology RN Wuerdig, F Baumgratz, S Bampi | | |
Ney Laert Vilar CalazansInvited Researcher at the Graduate Program on Microelectronics (PGMICRO), UFRGSVerified email at inf.ufrgs.br
