Nima Honarmand
Cited by
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DeNovo: Rethinking the memory hierarchy for disciplined parallelism
B Choi, R Komuravelli, H Sung, R Smolinski, N Honarmand, SV Adve, ...
2011 International Conference on Parallel Architectures and Compilation …, 2011
Safe nondeterminism in a deterministic-by-default parallel language
RL Bocchino Jr, S Heumann, N Honarmand, SV Adve, VS Adve, A Welc, ...
ACM SIGPLAN Notices 46 (1), 535-548, 2011
QuickRec: Prototyping an Intel architecture extension for record and replay of multithreaded programs
G Pokam, K Danne, C Pereira, R Kassa, T Kranich, S Hu, J Gottschlich, ...
Proceedings of the 40th annual international symposium on computer …, 2013
Hindsight: Understanding the evolution of ui vulnerabilities in mobile browsers
M Luo, O Starov, N Honarmand, N Nikiforakis
Proceedings of the 2017 ACM SIGSAC Conference on Computer and Communications …, 2017
Time does not heal all wounds: A longitudinal analysis of security-mechanism support in mobile browsers
M Luo, P Laperdrix, N Honarmand, N Nikiforakis
Proceedings of the 26th Network and Distributed System Security Symposium (NDSS), 2019
Cyrus: Unintrusive application-level record-replay for replay parallelism
N Honarmand, N Dautenhahn, J Torrellas, ST King, G Pokam, C Pereira
ACM SIGARCH Computer Architecture News 41 (1), 193-206, 2013
Replay debugging: Leveraging record and replay for program debugging
N Honarmand, J Torrellas
ACM SIGARCH Computer Architecture News 42 (3), 445-456, 2014
RelaxReplay: Record and replay for relaxed-consistency multiprocessors
N Honarmand, J Torrellas
Proceedings of the 19th international conference on Architectural support …, 2014
Taming the killer microsecond
S Cho, A Suresh, T Palit, M Ferdman, N Honarmand
2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018
Record-replay architecture as a general security framework
Y Shalabi, M Yan, N Honarmand, RB Lee, J Torrellas
2018 IEEE International Symposium on High Performance Computer Architecture …, 2018
Degradable mesh-based on-chip networks using programmable routing tables
A Shahabi, N Honarmand, H Sohofi, Z Navabi
IEICE Electronics Express 4 (10), 332-339, 2007
Low Power Combinational Multipliers using Data-driven Signal Gating
N Honarmand, A Afzali-Kusha
APCCAS 2006-2006 IEEE Asia Pacific Conference on Circuits and Systems, 1430-1433, 2006
High Level Synthesis of Degradable ASICs Using Virtual Binding
N Honarmand, A Shahabi, H Sohofi, M Abbaspour, Z Navabi
25th IEEE VLSI Test Symposium (VTS'07), 311-317, 2007
Asymmetric memory fences: Optimizing both performance and implementability
Y Duan, N Honarmand, J Torrellas
ACM SIGARCH Computer Architecture News 43 (1), 531-543, 2015
Power efficient sequential multiplication using pre-computation
N Honarmand, MR Javaheri, N Sedaghati-Mokhtari, A Afzali-Kusha
2006 IEEE International Symposium on Circuits and Systems, 4 pp., 2006
A heuristic search algorithm for re-routing of on-chip networks in the presence of faulty links and switches
N Honarmand, A Shahabi, Z Navabi
Proc. of IEEE EWDTS, 2007
Processor description in APDL for design space exploration of embedded processors
N Honarmand, H Sohofi, M Abbaspour, Z Navabi
Proc. EWDTS, 2007
Programmable routing tables for degradable torus-based networks on chips
A Shahabi, N Honarmand, Z Navabi
2007 IEEE International Symposium on Circuits and Systems (ISCAS), 1065-1068, 2007
Massively parallel server processors
V Agrawal, MA Dinani, Y Shui, M Ferdman, N Honarmand
IEEE Computer Architecture Letters 18 (1), 75-78, 2019
Memory Prefetching
N Honarmand
Jun 19, 33, 2015
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