| NCL synthesis with conventional EDA tools: Technology mapping and optimization MT Moreira, PA Beerel, MLL Sartori, NLV Calazans IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 1981-1993, 2017 | 21 | 2017 |
| Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC E Antunes, M Soares, A Aguiar, FS Johann, M Sartori, F Hessel, C Marcon Thirteenth International Symposium on Quality Electronic Design (ISQED), 451-457, 2012 | 17 | 2012 |
| Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations AF Gomez, F Lavratti, G Medeiros, M Sartori, LB Poehls, V Champac, ... Microelectronics Reliability 67, 150-158, 2016 | 16 | 2016 |
| Partitioning and mapping on NoC-based MPSoC: an energy consumption saving approach E Antunes, A Aguiar, FS Johann, M Sartori, F Hessel, C Marcon Proceedings of the 4th International Workshop on Network on Chip …, 2011 | 14 | 2011 |
| Data-driven risk stratification for preterm birth in Brazil: a population-based study to develop of a machine learning risk assessment approach TAH Rocha, EBAF de Thomaz, DG de Almeida, NC da Silva, ... The Lancet Regional Health–Americas 3, 2021 | 12 | 2021 |
| Pulsar: Constraining QDI circuits cycle time using traditional EDA tools MLL Sartori, RN Wuerdig, MT Moreira, NLV Calazans 2019 25th IEEE International Symposium on Asynchronous Circuits and Systems …, 2019 | 12 | 2019 |
| Early soft error reliability analysis on RISC-V N Lodéa, W Nunes, V Zanini, M Sartori, L Ost, N Calazans, R Garibotti, ... IEEE Latin America Transactions 20 (9), 2139-2145, 2022 | 11 | 2022 |
| A frontend using traditional EDA tools for the pulsar QDI design flow MLL Sartori, MT Moreira, NLV Calazans 2020 26th IEEE International Symposium on Asynchronous Circuits and Systems …, 2020 | 9 | 2020 |
| Adding virtualization support in mips 4kc-based mpsocs A Aguiar, C Moratelli, M Sartori, F Hessel Fifteenth International Symposium on Quality Electronic Design, 84-90, 2014 | 7 | 2014 |
| Leveraging qdi robustness to simplify the design of iot circuits MLL Sartori, RN Wuerdig, MT Moreira, S Bampi, NLV Calazans 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020 | 6 | 2020 |
| ASCEnDFreePDK45-A Free Standard Cell Library for SDDS-NCL Circuits MLL Sartori, MT Moreira, NLV Calazans Jun, 2020 | 6 | 2020 |
| Emergency care sensitive conditions in Brazil: a geographic information system approach to timely hospital access JE Isaacson, AP Joiner, AS Kozhumam, NM Caruzzo, L de Andrade, ... The Lancet Regional Health–Americas 4, 2021 | 5 | 2021 |
| Smart Check–COVID‐19 triage system: Evaluation of the impact on the screening time and identification of clinical manifestations of SARS‐CoV‐2 infection in a public health service F Anschau, PV Worm, L Kopittke, LH de Mello Villwock, ML Lemos Sartori, ... International Journal of Clinical Practice 75 (10), e14610, 2021 | 5 | 2021 |
| Pulsar-A Flow to Support the Design of QDI Asynchronous Circuits MLL Sartori, MT Moreira, NLV Calazans Pulsar-A Flow to Support the Design of QDI Asynchronous Circuits, 2020 | 5 | 2020 |
| Hardware-assisted virtualization targeting MIPS-based SoCs A Aguiar, C Moratelli, MLL Sartori, F Hessel 2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP), 2-8, 2012 | 5 | 2012 |
| A virtualization approach for MIPS-based MPSoCs A Aguiar, C Moratelli, MLL Sartori, F Hessel International Symposium on Quality Electronic Design (ISQED), 611-618, 2013 | 4 | 2013 |
| Mitigating asynchronous QDI drawbacks on MAC operators with approximate multipliers RN Wuerdig, MLL Sartori, BA Abreu, S Bampi, NLV Calazans 2022 IEEE International Symposium on Circuits and Systems (ISCAS), 1269-1273, 2022 | 3 | 2022 |
| Robust and energy-efficient hardware: the case for asynchronous design NLV Calazans, TA Rodolfo, MLL Sartori JICS. JOURNAL OF INTEGRATED CIRCUITS AND SYSTEMS (ED. PORTUGUÊS), 2021 | 3 | 2021 |
| Asynchronous Quasi-Random Number Generator: Taking Advantage of PVT Variations RN Wuerdig, MLL Sartori, NLV Calazans 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS), 137-140, 2019 | 3 | 2019 |
| Go functional model for a RISC-V asynchronous organisation—ARV MLL Sartori, NLV Calazans 2017 24th IEEE International Conference on Electronics, Circuits and Systems …, 2017 | 3 | 2017 |
Ney Laert Vilar CalazansInvited Researcher at the Graduate Program on Microelectronics (PGMICRO), UFRGSVerified email at inf.ufrgs.br
