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Bruno Canal
Bruno Canal
Federal University of Rio Grande do Sul, UFRGS
Verified email at restinga.ifrs.edu.br
Title
Cited by
Cited by
Year
Low-voltage dynamic comparator using positive feedback bulk effect on a floating inverter amplifier
B Canal, HD Klimach, S Bampi, TR Balen
Analog integrated circuits and signal processing 108 (3), 511-524, 2021
82021
Physical Implementation of a 32-bits RISC microprocessor using XFAB 600nm technology
B Canal, A Bonatto
32º SIMPOSIO SUL DE MICROELETRONICA, 1-4, 2017
42017
Hybrid Comparator and Window Switching Scheme for low-power SAR ADC
B Canal, H Klimach, S Bampi, TR Balen
2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 01-04, 2022
22022
Dança de robôs: uma atividade no meio escolar que integra robótica e ferramenta maker na perspectiva da aprendizagem criativa
CP Cabral, B Canal
Tecnologias, Sociedade e Conhecimento 7 (2), 122-142, 2020
22020
Standard Cell Library Validation Methodology
M de Carvalho, C Nunes, B Canal, L Puricelli, L Reinicke, G Webber
2
Low-Voltage Dynamic Comparator with Bulk-Driven Floating Inverter Amplifier
B Canal, HD Klimach, S Bampi, TR Balen
2020 33rd Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2020
12020
Time Assisted SAR ADC with Bit-guess and Digital Error Correction
B Canal, HD Klimach, S Bampi, TR Balen
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems …, 2022
2022
Designing a 9.3 μW Low-Power Time-to-Digital Converter (TDC) for a Time Assisted SAR ADC
RN Wuerdig, B Canal, TR Balen, S Bampi
2022 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems …, 2022
2022
Implementação física de um microprocessador Risc de 32-bits usando tecnologia XFAB 600nm
RYCJ Vieira, TC Tavares, KR Costa, SL Silva, B Canal, AC Bonatto
ScientiaTec 5 (2), 04-20, 2018
2018
CITest-Desenvolvimento de testes de circuitos integrados.
MC Diaz, AC Bonatto, B Canal
7º Seminário de Iniciação Científica e Tecnológica (SICT), 2018
2018
CITest: Desenvolvimento de Test board
TP Ribeiro, SL Silva, RYCJ Vieira, AC Bonatto, B Canal
7º Seminário de Iniciação Científica e Tecnológica (SICT), 2018
2018
CITest-Bring-up de circuito integrado
MC Diaz, AC Bonatto, B Canal
VIII Mostra Científica, 2018
2018
CITest-Desenvolvimento de um Test board
SL Silva, RYCJ Vieira, AC Bonatto, B Canal
VII Mostra Científica do IFRS-Campus Restinga, 2017
2017
Clube de Aeromodelismo–Controlador analógico para simulador
VD Possamai, RR da Silva Jardim, MR Muraro, B Canal
VII Mostra Científica do IFRS-Campus Restinga, 2017
2017
MCML gate design methodology ante the tradeoffs between MCML and CMOS applications
B Canal
2016
MCML gate design for standard cell library
B Canal, CS Nunes, RP Ribas, EE Fabris
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 1-6, 2015
2015
MCML Standard Cell Library: topologies analysis
B Canal, CS Nunes, RP Ribas, EE Fabris
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