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Alfio Di Mauro
Alfio Di Mauro
Integrated System Laboratory, ETH Zurich
Verified email at iis.ee.ethz.ch
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Cited by
Year
Quentin: an ultra-low-power pulpissimo soc in 22nm fdx
PD Schiavone, D Rossi, A Pullini, A Di Mauro, F Conti, L Benini
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
742018
Vega: A ten-core SoC for IoT endnodes with DNN acceleration and cognitive wake-up from MRAM-based state-retentive sleep mode
D Rossi, F Conti, M Eggiman, A Di Mauro, G Tagliavini, S Mach, ...
IEEE Journal of Solid-State Circuits 57 (1), 127-139, 2021
612021
Mr. wolf: A 1 gflop/s energy-proportional parallel ultra low power soc for iot edge processing
A Pullini, D Rossi, I Loi, A Di Mauro, L Benini
ESSCIRC 2018-IEEE 44th European Solid State Circuits Conference (ESSCIRC …, 2018
502018
Arnold: An eFPGA-augmented RISC-V SoC for flexible and low-power IoT end nodes
PD Schiavone, D Rossi, A Di Mauro, FK Gürkaynak, T Saxe, M Wang, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 29 (4), 677-690, 2021
422021
4.4 a 1.3 tops/w@ 32gops fully integrated 10-core soc for iot end-nodes with 1.7 μw cognitive wake-up from mram-based state-retentive sleep mode
D Rossi, F Conti, M Eggiman, S Mach, A Di Mauro, M Guermandi, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 60-62, 2021
422021
Always-on 674μ W@ 4GOP/s error resilient binary neural networks with aggressive SRAM voltage scaling on a 22-nm IoT end-node
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
IEEE Transactions on Circuits and Systems I: Regular Papers 67 (11), 3905-3918, 2020
362020
Kraken: A direct event/frame-based multi-sensor fusion soc for ultra-efficient visual processing in nano-uavs
A Di Mauro, M Scherer, D Rossi, L Benini
arXiv preprint arXiv:2209.01065, 2022
252022
Integrating event-based dynamic vision sensors with sparse hyperdimensional computing: a low-power accelerator with online learning capability
M Hersche, EM Rella, A Di Mauro, L Benini, A Rahimi
Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2020
222020
Sne: an energy-proportional digital accelerator for sparse event-based convolutions
A Di Mauro, AS Prasad, Z Huang, M Spallanzani, F Conti, L Benini
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 825-830, 2022
152022
A 1.15 TOPS/W, 16-cores parallel ultra-low power cluster with 2b-to-32b fully flexible bit-precision and vector lockstep execution mode
A Garofalo, G Ottavi, A Di Mauro, F Conti, G Tagliavini, L Benini, D Rossi
ESSCIRC 2021-IEEE 47th European Solid State Circuits Conference (ESSCIRC …, 2021
142021
An energy-efficient spiking neural network for finger velocity decoding for implantable brain-machine interface
J Liao, L Widmer, X Wang, A Di Mauro, SR Nason-Tomaszewski, ...
2022 IEEE 4th International Conference on Artificial Intelligence Circuits …, 2022
122022
22.1 A 12.4 TOPS/W@ 136GOPS AI-IoT system-on-chip with 16 RISC-V, 2-to-8b precision-scalable DNN acceleration and 30%-boost adaptive body biasing
F Conti, D Rossi, G Paulin, A Garofalo, A Di Mauro, G Rutishauer, ...
2023 IEEE International Solid-State Circuits Conference (ISSCC), 21-23, 2023
112023
Dustin: A 16-cores parallel ultra-low-power cluster with 2b-to-32b fully flexible bit-precision and vector Lockstep execution mode
G Ottavi, A Garofalo, G Tagliavini, F Conti, A Di Mauro, L Benini, D Rossi
IEEE Transactions on Circuits and Systems I: Regular Papers, 2023
92023
Independent body-biasing of pn transistors in an 28nm utbb fd-soi ulp near-threshold multi-core cluster
A Di Mauro, D Rossi, A Pullini, P Flatresse, L Benini
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018
92018
Pushing on-chip memories beyond reliability boundaries in micropower machine learning applications
A Di Mauro, F Conti, PD Schiavone, D Rossi, L Benini
2019 IEEE International Electron Devices Meeting (IEDM), 30.4. 1-30.4. 4, 2019
82019
A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications
M Scherer, A Di Mauro, G Rutishauser, T Fischer, L Benini
2022 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 1-3, 2022
72022
An ultra-low power address-event sensor interface for energy-proportional time-to-information extraction
A Di Mauro, F Conti, L Benini
Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017
72017
Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology
A Di Mauro, D Rossi, A Pullini, P Flatresse, L Benini
2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017
72017
Colibries: A milliwatts risc-v based embedded system leveraging neuromorphic and neural networks hardware accelerators for low-latency closed-loop control applications
G Rutishauser, R Hunziker, A Di Mauro, S Bian, L Benini, M Magno
2023 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2023
62023
Flydvs: An event-driven wireless ultra-low power visual sensor node
A Di Mauro, M Scherer, JF Mas, B Bougenot, M Magno, L Benini
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
62021
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