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Valeriya Kilchytska
Valeriya Kilchytska
Verified email at uclouvain.be
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Cited by
Year
INFLUENCE OF DEVICE ENGINEERING ON THE ANALOG AND RF PERFORMANCES OF SOI MOSFETS
V Kilchytska, A Neve, L Vancaillie, D Levacq, S Adriaensen, H van Meer, ...
Emerging nanoelectronics: life with and after CMOS 1, 375, 2005
2532005
Analog/RF performance of multiple gate SOI devices: wideband simulations and characterization
JP Raskin, TM Chung, V Kilchytska, D Lederer, D Flandre
IEEE Transactions on Electron Devices 53 (5), 1088-1095, 2006
1352006
FinFET analogue characterization from DC to 110 GHz
D Lederer, V Kilchytska, T Rudenko, N Collaert, D Flandre, A Dixit, ...
Solid-State Electronics 49 (9), 1488-1496, 2005
1262005
Gm/Id Method for Threshold Voltage Extraction Applicable in Advanced MOSFETs With Nonlinear Behavior Above Threshold
D Flandre, V Kilchytska, T Rudenko
Electron Device Letters, IEEE 31 (9), 930-932, 2010
872010
Compact model for highly-doped double-gate SOI MOSFETs targeting baseband analog applications
O Moldovan, A Cerdeira, D Jiménez, JP Raskin, V Kilchytska, D Flandre, ...
Solid-state electronics 51 (5), 655-661, 2007
752007
Effective mobility in FinFET structures with HfO2 and SiON gate dielectrics and TaN gate electrode
T Rudenko, N Collaert, S De Gendt, V Kilchytska, M Jurczak, D Flandre
Microelectronic Engineering 80, 386-389, 2005
682005
UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime
MKM Arshad, S Makovejev, S Olsen, F Andrieu, JP Raskin, D Flandre, ...
Solid-state electronics 90, 56-64, 2013
672013
A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs
H Abd El Hamid, JR Guitart, V Kilchytska, D Flandre, B Iñiguez
IEEE transactions on electron devices 54 (9), 2487-2496, 2007
662007
Perspective of FinFETs for analog applications
V Kilchytska, N Collaert, R Rooyackers, D Lederer, JP Raskin, D Flandre
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat …, 2004
662004
Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications
S Makovejev, BK Esfeh, V Barral, N Planes, M Haond, D Flandre, ...
Solid-State Electronics 108, 47-52, 2015
562015
On the MOSFET threshold voltage extraction by transconductance and transconductance-to-current ratio change methods: Part I—Effect of gate-voltage-dependent mobility
T Rudenko, V Kilchytska, MKM Arshad, JP Raskin, A Nazarov, D Flandre
IEEE Transactions on Electron Devices 58 (12), 4172-4179, 2011
542011
Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel
S Burignat, D Flandre, MKM Arshad, V Kilchytska, F Andrieu, O Faynot, ...
Solid-state electronics 54 (2), 213-219, 2010
532010
Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs
S Makovejev, JP Raskin, MKM Arshad, D Flandre, S Olsen, F Andrieu, ...
Solid-State Electronics 71, 93-100, 2012
522012
Floating effective back-gate effect on the small-signal output conductance of SOI MOSFETs
V Kilchytska, D Levacq, D Lederer, JP Raskin, D Flandre
IEEE Electron Device Letters 24 (6), 414-416, 2003
522003
On the MOSFET threshold voltage extraction by transconductance and transconductance-to-current ratio change methods: Part II—Effect of drain voltage
T Rudenko, V Kilchytska, MKM Arshad, JP Raskin, A Nazarov, D Flandre
IEEE Transactions on Electron Devices 58 (12), 4180-4188, 2011
512011
Time and frequency domain characterization of transistor self-heating
S Makovejev, SH Olsen, V Kilchytska, JP Raskin
IEEE transactions on electron devices 60 (6), 1844-1851, 2013
462013
Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit
V Kilchytska, MKM Arshad, S Makovejev, S Olsen, F Andrieu, T Poiroux, ...
Solid-State Electronics 70, 50-58, 2012
462012
Extended mastar modeling of dibl in utb and utbb soi mosfets
MKM Arshad, JP Raskin, V Kilchytska, F Andrieu, P Scheiblin, O Faynot, ...
IEEE transactions on electron devices 59 (1), 247-251, 2011
452011
Carrier mobility in undoped triple-gate FinFET structures and limitations of its description in terms of top and sidewall channel mobilities
T Rudenko, V Kilchytska, N Collaert, M Jurczak, A Nazarov, D Flandre
IEEE Transactions on Electron Devices 55 (12), 3532-3541, 2008
452008
On the high-temperature subthreshold slope of thin-film SOI MOSFETs
T Rudenko, V Kilchytska, JP Colinge, V Dessard, D Flandre
IEEE Electron Device Letters 23 (3), 148-150, 2002
452002
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