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Shankar Ganesh Ramasubramanian
Shankar Ganesh Ramasubramanian
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Cited by
Cited by
Year
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing
SG Ramasubramanian, R Venkatesan, M Sharad, K Roy, A Raghunathan
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
1042014
STAG: Spintronic-Tape Architecture for GPGPU cache hierarchies
R Venkatesan, SG Ramasubramanian, S Venkataramani, K Roy, ...
Computer Architecture (ISCA), 2014 ACM/IEEE 41st International Symposium on …, 2014
872014
Relax-and-retime: a methodology for energy-efficient recovery based design
SG Ramasubramanian, S Venkataramani, A Parandhaman, ...
Proceedings of the 50th Annual Design Automation Conference, 111, 2013
502013
DyReCTape: a dynamically reconfigurable cache using domain wall memory tapes
A Ranjan, SG Ramasubramanian, R Venkatesan, V Pai, K Roy, ...
Proceedings of the 2015 Design, Automation & Test in Europe Conference …, 2015
202015
Minimal Aliasing Single-Error-Correction Codes for DRAM Reliability Improvement
SI Pae, V Kozhikkottu, D Somasekar, W Wu, SG Ramasubramanian, ...
IEEE Access 9, 29862-29869, 2021
92021
Minimal aliasing bit-error correction code
D Somasekhar, W Wu, SG Ramasubramanian, V Kozhikkottu, M Dadual
US Patent 10,860,419, 2020
62020
Automatic Synthesis Techniques for Approximate Circuits
A Ranjan, S Venkataramani, S Jain, Y Kim, SG Ramasubramanian, ...
Approximate Circuits, 123-140, 2019
42019
Increasing read pending queue capacity to increase memory bandwidth
G Koo, V Kozhikkottu, SG Ramasubramanian, CB Wilkerson
US Patent App. 15/395,615, 2018
32018
Generating synthetic benchmark circuits for accelerated life testing of field programmable gate arrays using genetic algorithm and particle swarm optimization
L Srivani, NHVK Giri, S Ganesh, V Kamakoti
Applied Soft Computing 27, 179-190, 2015
22015
Full duplex dram for tightly coupled compute die and memory die
RB Osborne, CP Mozak, SG Ramasubramanian
US Patent App. 17/892,000, 2022
2022
Programmable data bus inversion and configurable implementation
M Dadual, VJ Kozhikkottu, SG Ramasubramanian
US Patent 11,281,616, 2022
2022
Techniques for setting a 2-level auto-close timer to access a memory device
V Kozhikkottu, S Chittor, E Choukse, SG Ramasubramanian
US Patent 11,216,386, 2022
2022
System, apparatus and method for application specific address mapping
V Kozhikkottu, E Choukse, SG Ramasubramanian, M Dadual, S Chittor
US Patent 10,936,507, 2021
2021
Error correction code (ECC) and data bus inversion (DBI) encoding
VJ Kozhikkottu, SG Ramasubramanian, D Somasekhar, M Dadual
US Patent 10,862,622, 2020
2020
Low latency statistical data bus inversion for energy reduction
V Kozhikkottu, SG Ramasubramanian, K Kwon, D Somasekhar
US Patent 10,853,300, 2020
2020
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