| Method for design optimization using logical and physical information L Pileggi, M Sarrafzadeh, S Malik, A Chakraborty, A Li, RE Shortt, C Dunn, ... US Patent 6,286,128, 2001 | 154 | 2001 |
| Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture B Gaide, D Gaitonde, C Ravishankar, T Bauer Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 143 | 2019 |
| Network-on-Chip Programmable Platform in VersalTM ACAP Architecture I Swarbrick, D Gaitonde, S Ahmad, B Gaide, Y Arbel Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019 | 54 | 2019 |
| Hierarchical mapping of spot defects to catastrophic faults-design and applications DD Gaitonde, DMH Walker IEEE Transactions on Semiconductor Manufacturing 8 (2), 167-177, 1995 | 31 | 1995 |
| Enhancements in UltraScale CLB architecture S Chandrakar, D Gaitonde, T Bauer Proceedings of the 2015 ACM/SIGDA International Symposium on Field …, 2015 | 30 | 2015 |
| Boolean satisfiability-based routing and its application to xilinx ultrascale clock network H Fraisse, A Joshi, D Gaitonde, A Kaviani Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016 | 25 | 2016 |
| A domain-specific architecture for accelerating sparse matrix vector multiplication on fpgas AK Jain, H Omidian, H Fraisse, M Benipal, L Liu, D Gaitonde 2020 30th International conference on field-programmable logic and …, 2020 | 22 | 2020 |
| Placement strategies for 2.5 D FPGA fabric architectures C Ravishankar, D Gaitonde, T Bauer 2018 28th International Conference on Field Programmable Logic and …, 2018 | 18 | 2018 |
| Versal network-on-chip (NoC) I Swarbrick, D Gaitonde, S Ahmad, B Jayadev, J Cuppett, A Morshed, ... 2019 IEEE Symposium on High-Performance Interconnects (HOTI), 13-17, 2019 | 15 | 2019 |
| Test quality and yield analysis using the DEFAM defect to fault mapper DD Gaitonde, DMH Walker Proceedings of 1993 International Conference on Computer Aided Design (ICCAD …, 1993 | 14 | 1993 |
| Clock network architecture BC Gaide, SP Young, TJ Bauer, RM Ondris, DD Gaitonde US Patent 8,937,491, 2015 | 12 | 2015 |
| Circuit-level modeling of spot defects D Gaitonde, DMH Walker 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems …, 1991 | 12 | 1991 |
| A SAT-based timing driven place and route flow for critical soft IP H Fraisse, D Gaitonde 2018 28th International Conference on Field Programmable Logic and …, 2018 | 8 | 2018 |
| Sparse deep neural network acceleration on HBM-enabled FPGA platform AK Jain, S Kumar, A Tripathi, D Gaitonde 2021 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2021 | 7 | 2021 |
| Clock speed for a digital circuit S Srinivasan, DD Gaitonde US Patent 8,024,696, 2011 | 7 | 2011 |
| Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits SR Raje, LT Pileggi, DD Gaitonde, OR Coudert, P Gopalakrishnan, ... US Patent 6,775,808, 2004 | 7 | 2004 |
| Estimation of reject ratio in testing of combinatorial circuits DD Gaitonde, J Khare, DMH Walker, W Maly Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium, 319-325, 1993 | 7 | 1993 |
| Configurable network-on-chip for a programmable device IA Swarbrick, S Ahmad, Y Arbel, DD Gaitonde US Patent 10,838,908, 2020 | 6 | 2020 |
| Fault probability prediction for array based designs DD Gaitonde, W Maly, DMH Walker Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance …, 1996 | 6 | 1996 |
| Accurate yield estimation of circuits with redundancy DD Gaitonde, DMH Walker, W Maly Proceedings of International Workshop on Defect and Fault Tolerance in VLSI …, 1995 | 6 | 1995 |
