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pierpaolo palestri
pierpaolo palestri
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Cited by
Year
Electromechanical piezoresistive sensing in suspended graphene membranes
AD Smith, F Niklaus, A Paussa, S Vaziri, AC Fischer, M Sterner, ...
Nano letters 13 (7), 3237-3242, 2013
3542013
Nanoscale MOS transistors: semi-classical transport and applications
D Esseni, P Palestri, L Selmi
Cambridge University Press, 2011
2362011
Understanding quasi-ballistic transport in nano-MOSFETs: part I-scattering in the channel and in the drain
P Palestri, D Esseni, S Eminente, C Fiegna, E Sangiorgi, L Selmi
IEEE Transactions on Electron Devices 52 (12), 2727-2735, 2005
1822005
Investigation of the transport properties of silicon nanowires using deterministic and Monte Carlo approaches to the solution of the Boltzmann transport equation
M Lenzi, P Palestri, E Gnani, S Reggiani, A Gnudi, D Esseni, L Selmi, ...
IEEE Transactions on Electron Devices 55 (8), 2086-2096, 2008
1072008
Multisubband Monte Carlo study of transport, quantization, and electron-gas degeneration in ultrathin SOI n-MOSFETs
L Lucci, P Palestri, D Esseni, L Bergagnini, L Selmi
IEEE transactions on electron devices 54 (5), 1156-1164, 2007
1052007
Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture
R Nonis, N Da Dalt, P Palestri, L Selmi
IEEE Journal of Solid-State Circuits 40 (6), 1303-1309, 2005
812005
Impact of TFET unidirectionality and ambipolarity on the performance of 6T SRAM cells
S Strangio, P Palestri, D Esseni, L Selmi, F Crupi, S Richter, QT Zhao, ...
IEEE Journal of the Electron Devices Society 3 (3), 223-232, 2015
742015
Understanding quasi-ballistic transport in nano-MOSFETs: Part II-Technology scaling along the ITRS
S Eminente, D Esseni, P Palestri, C Fiegna, L Selmi, E Sangiorgi
IEEE transactions on electron devices 52 (12), 2736-2743, 2005
732005
A design methodology for MOS current-mode logic frequency dividers
R Nonis, E Palumbo, P Palestri, L Selmi
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (2), 245-254, 2007
722007
Compact modeling of thermal resistance in bipolar transistors on bulk and SOI substrates
A Pacelli, P Palestri, M Mastrapasqua
IEEE Transactions on Electron Devices 49 (6), 1027-1033, 2002
712002
Closed-and open-boundary models for gate-current calculation in n-MOSFETs
A Dalla Serra, A Abramo, P Palestri, L Selmi, F Widdershoven
IEEE Transactions on Electron Devices 48 (8), 1811-1815, 2001
702001
An improved semi-classical Monte-Carlo approach for nano-scale MOSFET simulation
P Palestri, S Eminente, D Esseni, C Fiegna, E Sangiorgi, L Selmi
Solid-state electronics 49 (5), 727-732, 2005
692005
A TCAD-based methodology to model the site-binding charge at ISFET/electrolyte interfaces
A Bandiziol, P Palestri, F Pittino, D Esseni, L Selmi
IEEE Transactions on Electron Devices 62 (10), 3379-3386, 2015
682015
Mixed tunnel-FET/MOSFET level shifters: A new proposal to extend the tunnel-FET application domain
M Lanuzza, S Strangio, F Crupi, P Palestri, D Esseni
IEEE Transactions on Electron Devices 62 (12), 3973-3979, 2015
652015
Linear combination of bulk bands method for investigating the low-dimensional electron gas in nanostructured devices
D Esseni, P Palestri
Physical Review B 72 (16), 165342, 2005
652005
On the apparent mobility in nanometric n-MOSFETs
M Zilli, D Esseni, P Palestri, L Selmi
IEEE Electron Device Letters 28 (11), 1036-1039, 2007
602007
A review of selected topics in physics based modeling for tunnel field-effect transistors
D Esseni, M Pala, P Palestri, C Alper, T Rollo
Semiconductor Science and Technology 32 (8), 083005, 2017
582017
Understanding the potential and limitations of tunnel FETs for low-voltage analog/mixed-signal circuits
F Settino, M Lanuzza, S Strangio, F Crupi, P Palestri, D Esseni, L Selmi
IEEE Transactions on Electron Devices 64 (6), 2736-2743, 2017
552017
Experimental and simulation analysis of program/retention transients in silicon nitride-based NVM cells
E Vianello, F Driussi, A Arreghini, P Palestri, D Esseni, L Selmi, N Akil, ...
IEEE transactions on electron devices 56 (9), 1980-1990, 2009
552009
Explanation of the charge trapping properties of silicon nitride storage layers for NVMs—Part II: Atomistic and electrical modeling
E Vianello, F Driussi, P Blaise, P Palestri, D Esseni, L Perniola, G Molas, ...
IEEE Transactions on Electron Devices 58 (8), 2490-2499, 2011
542011
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