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Morin Dehan
Morin Dehan
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Verified email at sony.com
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Design issues and considerations for low-cost 3-D TSV IC technology
G Van der Plas, P Limaye, I Loi, A Mercha, H Oprins, C Torregiani, S Thijs, ...
IEEE Journal of Solid-State Circuits 46 (1), 293-307, 2010
3872010
Influence of device engineering on the analog and RF performances of SOI MOSFETs
V Kilchytska, A Neve, L Vancaillie, D Levacq, S Adriaensen, H van Meer, ...
IEEE Transactions on Electron Devices 50 (3), 577-588, 2003
2662003
Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective
V Subramanian, B Parvais, J Borremans, A Mercha, D Linten, P Wambacq, ...
IEEE Transactions on Electron Devices 53 (12), 3071-3079, 2006
1892006
What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?
G Dambrine, C Raynaud, D Lederer, M Dehan, O Rozeaux, ...
IEEE Electron Device Letters 24 (3), 189-191, 2003
1322003
Impact of fin width on digital and analog performances of n-FinFETs
V Subramanian, A Mercha, B Parvais, J Loo, C Gustin, M Dehan, ...
Solid-State Electronics 51 (4), 551-559, 2007
1142007
Fully depleted SOI CMOS technology for heterogeneous micropower, high-temperature or RF microsystems
D Flandre, S Adriaensen, A Akheyar, A Crahay, L Demeûs, P Delatte, ...
Solid-State Electronics 45 (4), 541-549, 2001
1132001
VCO design for 60 GHz applications using differential shielded inductors in 0.13 μm CMOS
J Borremans, M Dehan, K Scheir, M Kuijk, P Wambacq
2008 IEEE Radio Frequency Integrated Circuits Symposium, 135-138, 2008
752008
Gate-last vs. gate-first technology for aggressively scaled EOT logic/RF CMOS
A Veloso, LĊ Ragnarsson, MJ Cho, K Devriendt, K Kellens, F Sebaai, ...
2011 Symposium on VLSI Technology-Digest of Technical Papers, 34-35, 2011
682011
A compact wideband front-end using a single-inductor dual-band VCO in 90 nm digital CMOS
J Borremans, A Bevilacqua, S Bronckers, M Dehan, M Kuijk, P Wambacq, ...
IEEE Journal of Solid-State Circuits 43 (12), 2693-2705, 2008
612008
The potential of FinFETs for analog and RF circuit applications
P Wambacq, B Verbruggen, K Scheir, J Borremans, M Dehan, D Linten, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2541-2551, 2007
592007
Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs
V Subramaniana, B Parvais, J Borremans, A Mercha, D Linten, ...
IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005
592005
Vertical nanowire FET integration and device aspects
A Veloso, E Altamirano-Sánchez, S Brus, BT Chan, M Cupak, M Dehan, ...
ECS Transactions 72 (4), 31, 2016
532016
T-diodes-a novel plug-and-play wideband RF circuit ESD protection methodology
D Linten, S Thijs, J Borremans, M Dehan, D Tremouilles, M Scholz, ...
2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD …, 2007
512007
Stochastic matching properties of FinFETs
C Gustin, A Mercha, J Loo, V Subramanian, B Parvais, M Dehan, ...
IEEE Electron Device Letters 27 (10), 846-848, 2006
472006
Identifying the bottlenecks to the RF performance of FinFETs
V Subramanian, A Mercha, B Parvais, M Dehan, G Groeseneken, ...
2010 23rd International Conference on VLSI Design, 111-116, 2010
452010
Matching performance of FinFET devices with fin widths down to 10 nm
P Magnone, A Mercha, V Subramanian, P Parvais, N Collaert, M Dehan, ...
IEEE electron device letters 30 (12), 1374-1376, 2009
442009
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
MG Bardon, V Moroz, G Eneman, P Schuddinck, M Dehan, D Yakimets, ...
2013 Symposium on VLSI Technology, T114-T115, 2013
392013
Layout-induced stress effects in 14nm & 10nm FinFETs and their impact on performance
MG Bardon, V Moroz, G Eneman, P Schuddinck, M Dehan, D Yakimets, ...
39*
An asymmetric channel SOI nMOSFET for improving DC and microwave characteristics
M Dehan, JP Raskin
Solid-State Electronics 46 (7), 1005-1011, 2002
352002
Characterization and modeling of SOI RF integrated components
M Dehan
Presses univ. de Louvain, 2003
332003
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