| Effectiveness of a hardware-based approach to detect resistive-open defects in SRAM cells under process variations AF Gomez, F Lavratti, G Medeiros, M Sartori, LB Poehls, V Champac, ... Microelectronics Reliability 67, 150-158, 2016 | 16 | 2016 |
| Early selection of critical paths for reliable NBTI aging-delay monitoring AF Gomez, V Champac IEEE Transactions on very large scale integration (VLSI) systems 24 (7 …, 2016 | 16 | 2016 |
| A new sizing approach for lifetime improvement of nanoscale digital circuits due to BTI aging A Gomez, V Champac 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 9 | 2015 |
| Selection of critical paths for reliable frequency scaling under BTI-aging considering workload uncertainty and process variations effects AF Gomez, V Champac ACM Transactions on Design Automation of Electronic Systems (TODAES) 23 (3 …, 2018 | 8 | 2018 |
| An efficient metric-guided gate sizing methodology for guardband reduction under process variations and aging effects A Gomez, V Champac Journal of Electronic Testing 35, 87-100, 2019 | 6 | 2019 |
| Effective selection of favorable gates in BTI-critical paths to enhance circuit reliability A Gomez, V Champac 2015 16th Latin-American Test Symposium (LATS), 1-6, 2015 | 6 | 2015 |
| Robust detection of bridge defects in STT-MRAM cells under process variations AF Gomez, F Forero, K Roy, V Champac 2018 IFIP/IEEE International Conference on Very Large Scale Integration …, 2018 | 4 | 2018 |
| An early prediction methodology for aging sensor insertion to assure safe circuit operation due to NBTI aging A Gomez, L Poehls, F Vargas, V Champac 2015 IEEE 33rd VLSI Test Symposium (VTS), 1-6, 2015 | 4 | 2015 |
| Analysis of bridge defects in STT-MRAM cells under process variations and a robust DFT technique for their detection V Champac, A Gomez, F Forero, K Roy VLSI-SoC: Design and Engineering of Electronics Systems Based on New …, 2019 | 3 | 2019 |
| A metric-guided gate-sizing methodology for aging guardband reduction AF Gomez, R Gomez, V Champac 2018 IEEE 19th Latin-American Test Symposium (LATS), 1-6, 2018 | 3 | 2018 |
| Circuit performance optimization for local intra-die process variations using a gate selection metric V Champac, AN Reyes, AF Gomez 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 3 | 2015 |
| Critical path selection under NBTI/PBTI aging for adaptive frequency tuning AF Gomez, V Champac 2016 IEEE East-West Design & Test Symposium (EWDTS), 1-4, 2016 | 1 | 2016 |
| A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage F Forero, A Gomez, V Champac 2016 17th Latin-American Test Symposium (LATS), 81-86, 2016 | 1 | 2016 |
| Improvement of Negative Bias Temperature Instability Circuit Reliability and Power Consumption Using Dual Supply Voltage F Forero, A Gomez, V Champac Journal of Low Power Electronics 12 (4), 395-402, 2016 | | 2016 |
| Cahier des charges “Telares Mandy” A Artamonova, A Gómez, C Romero | | |
| Espirómetro Electrónico Portátil con Visualización en Dispositivo Móvil RDVPS Vera, A Gomez | | |
| A Metric-Guided Circuit Design Methodology for Aging Guardband Compensation A Gomez, V Champac | | |
Champac VINAOEVerified email at inaoep.mx
Champac VINAOEVerified email at inaoep.mx
Marcos SartoriPUCRSVerified email at acad.pucrs.br