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In-Cheol Park
In-Cheol Park
Professor of Electrical Engineering, KAIST
Verified email at kaist.edu - Homepage
Title
Cited by
Cited by
Year
A single-chip programmable platform based on a multithreaded processor and configurable logic clusters
YD Bae, SI Park, IC Park
IEEE Journal of Solid-State Circuits 38 (10), 1703-1711, 2003
2302003
Digital filter synthesis based on minimal signed digit representation
IC Park, HJ Kang
Proceedings of the 38th annual Design Automation Conference, 468-473, 2001
1622001
FIR filter synthesis algorithms for minimizing the delay and the number of adders
HJ Kang, IC Park
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal …, 2001
1502001
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
IC Park, HJ Kang
IEEE transactions on computer-aided design of integrated circuits and …, 2002
1352002
Synthesis of application specific instructions for embedded DSP software
H Choi, SH Hwang, CM Kyung, IC Park
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided …, 1998
1251998
SAT-based unbounded symbolic model checking
HJ Kang, IC Park
Proceedings of the 40th annual Design Automation Conference, 840-843, 2003
1082003
High-performance and low-power memory interface architecture for video processing applications
H Kim, IC Park
Circuits and Systems for Video Technology, IEEE Transactions on 11 (11 …, 2001
1082001
A unified parallel radix-4 turbo decoder for mobile WiMAX and 3GPP-LTE
JH Kim, IC Park
2009 IEEE Custom Integrated Circuits Conference, 487-490, 2009
992009
Loosely coupled memory-based decoding architecture for low density parity check codes
SH Kang, IC Park
IEEE Transactions on Circuits and Systems I: Regular Papers 53 (5), 1045-1056, 2006
942006
Loosely Coupled Memory-Based Decoding Architecture for Low Density Parity Check Codes
SH Kang, IC Park
IEEE Custom Integrated Circuit Conf, 703-706, 2005
942005
Balanced binary-tree decomposition for area-efficient pipelined FFT processing
HY Lee, IC Park
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (4), 889-900, 2007
862007
6.4 Gb/s multi-threaded BCH encoder and decoder for multi-channel SSD controllers
Y Lee, H Yoo, I Yoo, IC Park
2012 IEEE International Solid-State Circuits Conference, 426-428, 2012
852012
Improving dictionary-based code compression in VLIW architectures
SJ Nam, IC Park, CM Kyung
IEICE Trans. Fundamentals 82 (11), 2318-2324, 1999
781999
DSIP: A scalable inference accelerator for convolutional neural networks
J Jo, S Cha, D Rho, IC Park
IEEE Journal of Solid-State Circuits 53 (2), 605-618, 2017
692017
A 210mW Graphics LSI Implementation Full 3D Pipeline with 264Mtexels/s Texturing for Mobile Multimedia Applications
R Woo, S Choi, JH Sohn, SJ Song, YD Bae, CW Yoon, BG Nam, JH Woo, ...
IEEE Int. Solid-State Circuits Conf, 44-476, 2003
692003
Spur-free MASH delta-sigma modulation
J Song, IC Park
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (9), 2426-2437, 2010
682010
Apparatus and method of multiplication using a plurality of identical partial multiplication modules
WK Cho, JW Kim, I Park, E Lee, H Kang
US Patent 7,769,797, 2010
632010
Method of decoding bin values using pipeline architecture and decoding device therefor
I Park, Y Yi
US Patent 7,411,529, 2008
622008
Energy-efficient convolution architecture based on rescheduled dataflow
J Jo, S Kim, IC Park
IEEE Transactions on Circuits and Systems I: Regular Papers 65 (12), 4196-4207, 2018
602018
Fast and near optimal scheduling in automatic data path synthesis
IC Park, CM Kyung
Proceedings of the 28th ACM/IEEE Design Automation Conference, 680-685, 1991
601991
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Articles 1–20