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Jorge Echavarria
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FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs
J Echavarria, S Wildermann, A Becher, J Teich, D Ziener
2016 International Conference on Field-Programmable Technology (FPT), 213-216, 2016
212016
A LUT-based approximate adder
A Becher, J Echavarria, D Ziener, S Wildermann, J Teich
2016 IEEE 24th Annual International Symposium on Field-Programmable Custom …, 2016
192016
Design space exploration of multi-output logic function approximations
J Echavarria, S Wildermann, J Teich
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018
122018
Efficient arithmetic error rate calculus for visibility reduced approximate adders
J Echavarria, S Wildermann, E Potwigin, J Teich
IEEE Embedded Systems Letters 10 (2), 37-40, 2017
102017
FSM merging and reduction for IP cores watermarking using genetic algorithms
J Echavarria, A Morales-Reyes, R Cumplido, MA Salido
2014 International Conference on ReConFigurable Computing and FPGAs …, 2014
102014
Probabilistic error propagation through approximated Boolean networks
J Echavarria, S Wildermann, O Keszöcze, J Teich
2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020
72020
Emerging Computing Devices: Challenges and Opportunities for Test and Reliability*
A Bosio, I O’Connor, M Traiola, J Echavarria, J Teich, MA Hanif, ...
2021 IEEE European Test Symposium (ETS), 1-10, 2021
52021
Can Approximate Computing Reduce Power Consumption on FPGAs?
J Echavarria, K Schütz, A Becher, S Wildermann, J Teich
2018 25th IEEE International Conference on Electronics, Circuits and Systems …, 2018
32018
Self-adaptive FPGA-based image processing filters using approximate arithmetics
J Pirkl, A Becher, J Echavarria, J Teich, S Wildermann
Proceedings of the 20th International Workshop on Software and Compilers for …, 2017
32017
Approximate Logic Synthesis of Very Large Boolean Networks
J Echavarria, S Wildermann, J Teich
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2021
22021
Evaluation of Approximate Computing Techniques for Power Reduction on FPGAs
J Echavarria, K Schütz, A Becher, S Wildermann, J Teich
AxC18: 3rd Workshop on Approximate Computing, 2018
22018
IP-cores watermarking scheme at behavioral level using genetic algorithms
J Echavarria, A Morales-Reyes, R Cumplido, MA Salido, ...
Engineering Applications of Artificial Intelligence 104, 104386, 2021
12021
AConFPGA: A Multiple-Output Boolean Function Approximation DSE Technique Targeting FPGAs
J Echavarria, S Wildermann, J Teich
2018 International Conference on Field-Programmable Technology (FPT), 326-329, 2018
12018
Probability-Based DSE of Approximated LUT-Based FPGA Designs
J Echavarria, O Keszocze, J Teich
2022 IEEE 15th Dallas Circuit And System Conference (DCAS), 1-5, 2022
2022
Design and error analysis of accuracy-configurable sequential multipliers via segmented carry chains
J Echavarria, S Wildermann, O Keszocze, F Khosravi, A Becher, J Teich
it-Information Technology 64 (3), 89-98, 2022
2022
Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits
M Traiola, J Echavarria, A Bosio, J Teich, I O'Connor
2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-9, 2021
2021
On the Approximation of Accuracy-configurable Sequential Multipliers via Segmented Carry Chains
J Echavarria, S Wildermann, O Keszocze, F Khosravi, A Becher, J Teich
arXiv preprint arXiv:2105.05588, 2021
2021
Approximate Adder Structures on FPGAs
A Becher, J Echavarria, D Ziener, J Teich
Workshop on Approximate Computing 2015, 2015
2015
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Articles 1–18