| Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes H Cronie, A Shokrollahi, A Tajalli US Patent 8,649,445, 2014 | 164 | 2014 |
| Subthreshold source-coupled logic circuits for ultra-low-power applications A Tajalli, EJ Brauer, Y Leblebici, E Vittoz IEEE Journal of Solid-State Circuits 43 (7), 1699-1710, 2008 | 141 | 2008 |
| Implementing ultra-high-value floating tunable CMOS resistors A Tajalli, Y Leblebici, EJ Brauer IEE Electronics Letters 44 (ARTICLE), 349-350, 2008 | 136 | 2008 |
| Efficient processing and detection of balanced codes A Tajalli, H Cronie, A Shokrollahi US Patent 8,593,305, 2013 | 134 | 2013 |
| Extreme low-power mixed signal IC design: subthreshold source-coupled circuits A Tajalli, Y Leblebici Springer Science & Business Media, 2010 | 84 | 2010 |
| Methods and systems for noise resilient, pin-efficient and low power communications with sparse signaling codes H Cronie, A Shokrollahi, A Tajalli US Patent 9,154,252, 2015 | 82 | 2015 |
| Symmetric is linear equalization circuit with increased gain A Tajalli US Patent 9,148,087, 2015 | 82 | 2015 |
| A review on quantum computing: From qubits to front-end electronics and cryogenic MOSFET physics F Jazaeri, A Beckers, A Tajalli, JM Sallese 2019 MIXDES-26th International Conference" Mixed Design of Integrated …, 2019 | 76 | 2019 |
| Design trade-offs in ultra-low-power digital nanoscale CMOS A Tajalli, Y Leblebici IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 2189-2200, 2011 | 71 | 2011 |
| High performance phase locked loop A Tajalli US Patent 10,057,049, 2018 | 69 | 2018 |
| A Slew Controlled LVDS Output Driver Circuit in 0.18 m CMOS Technology A Tajalli, Y Leblebici IEEE journal of solid-state circuits 44 (2), 538-548, 2009 | 63 | 2009 |
| Vector signaling codes for densely-routed wire groups A Shokrollahi, A Hormati, A Tajalli US Patent 10,333,741, 2019 | 56 | 2019 |
| 10.1 A pin-efficient 20.83 Gb/s/wire 0.94 pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS A Shokrollahi, D Carnelli, J Fox, K Hofstra, B Holden, A Hormati, P Hunt, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 182-183, 2016 | 52 | 2016 |
| High speed communications system A Hormati, A Tajalli, A Shokrollahi US Patent 9,832,046, 2017 | 45 | 2017 |
| Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept A Tajalli, E Vittoz, Y Leblebici, EJ Brauer ESSCIRC 2007-33rd European Solid-State Circuits Conference, 304-307, 2007 | 40 | 2007 |
| Lock detector for phase lock loop A Tajalli US Patent 9,906,358, 2018 | 38 | 2018 |
| Voltage sampler driver with enhanced high-frequency gain A Tajalli US Patent 10,003,315, 2018 | 37 | 2018 |
| Ultra low power subthreshold current-mode logic utilizing a novel PMOS load device A Tajalli, E Vittoz, Y Leblebici, E Brauer IEE Electronics Letters 43 (ARTICLE), 911-913, 2007 | 36 | 2007 |
| Leakage current reduction using subthreshold source-coupled logic A Tajalli, Y Leblebici IEEE Transactions on Circuits and Systems II: Express Briefs 56 (5), 374-378, 2009 | 35 | 2009 |
| Methods and systems for providing multi-stage distributed decision feedback equalization A Tajalli US Patent 10,326,623, 2019 | 31 | 2019 |
Yusuf LeblebiciProfessor of Electrical Engineering, EPFLVerified email at epfl.ch
