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Chih-Cheng Hsieh
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Focal-plane-arrays and CMOS readout techniques of infrared imaging systems
CC Hsieh, CY Wu, FW Jih, TP Sun
IEEE Transactions on Circuits and Systems for Video Technology 7 (4), 594-605, 1997
2901997
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
WH Chen, KX Li, WY Lin, KH Hsu, PY Li, CH Yang, CX Xue, EY Yang, ...
2018 IEEE International Solid-State Circuits Conference-(ISSCC), 494-496, 2018
2572018
24.1 A 1Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors
CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 388-390, 2019
2162019
24.5 A twin-8T SRAM computation-in-memory macro for multiple-bit CNN-based machine learning
X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ...
2019 IEEE International Solid-State Circuits Conference-(ISSCC), 396-398, 2019
1802019
15.4 A 22nm 2Mb ReRAM compute-in-memory macro with 121-28TOPS/W for multibit MAC computing for tiny AI edge devices
CX Xue, TY Huang, JS Liu, TW Chang, HY Kao, JH Wang, TW Liu, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 244-246, 2020
1522020
A 2.4-to-5.2 fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with charge-average switching DAC in 90nm CMOS
CY Liou, CC Hsieh
2013 ieee international solid-state circuits conference digest of technical …, 2013
1362013
15.5 A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips
X Si, YN Tu, WH Huang, JW Su, PJ Lu, JH Wang, TW Liu, SY Wu, R Liu, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 246-248, 2020
1232020
CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors
WH Chen, C Dou, KX Li, WY Lin, PY Li, JH Huang, JH Wang, WC Wei, ...
Nature Electronics 2 (9), 420-428, 2019
1222019
15.2 a 28nm 64Kb inference-training two-way transpose multibit 6T SRAM Compute-in-Memory macro for AI edge chips
JW Su, X Si, YC Chou, TW Chang, WH Huang, YN Tu, R Liu, PJ Lu, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 240-242, 2020
1112020
A 0.3 V 10-bit 1.17 f SAR ADC with merge and split switching in 90 nm CMOS
JY Lin, CC Hsieh
IEEE Transactions on Circuits and Systems I: Regular Papers 62 (1), 70-79, 2014
992014
A twin-8T SRAM computation-in-memory unit-macro for multibit CNN-based AI edge processors
X Si, JJ Chen, YN Tu, WH Huang, JH Wang, YC Chiu, WC Wei, SY Wu, ...
IEEE Journal of Solid-State Circuits 55 (1), 189-202, 2019
972019
A new cryogenic CMOS readout structure for infrared focal plane array
CC Hsieh, CY Wu, TP Sun
IEEE Journal of Solid-State Circuits 32 (8), 1192-1199, 1997
961997
High-performance CMOS buffered gate modulation input (BGMI) readout circuits for IR FPA
CC Hsieh, CY Wu, TP Sun, FW Jih, YT Cherng
IEEE journal of solid-state circuits 33 (8), 1188-1198, 1998
851998
16.1 A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices
CX Xue, JM Hung, HY Kao, YH Huang, SP Huang, FC Chang, P Chen, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 245-247, 2021
812021
A 2.02–5.16 fJ/conversion step 10 bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS
YJ Chen, KH Chang, CC Hsieh
IEEE Journal of Solid-State Circuits 51 (2), 357-364, 2015
742015
16.3 A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips
JW Su, YC Chou, R Liu, TW Liu, PJ Lu, PC Wu, YL Chung, LY Hung, ...
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 250-252, 2021
642021
A 0.44-fJ/conversion-step 11-bit 600-kS/s SAR ADC with semi-resting DAC
SE Hsieh, CC Hsieh
IEEE Journal of Solid-State Circuits 53 (9), 2595-2603, 2018
632018
A low-power electronic nose signal-processing chip for a portable artificial olfaction system
KT Tang, SW Chiu, MF Chang, CC Hsieh, JM Shyu
IEEE transactions on biomedical circuits and systems 5 (4), 380-390, 2011
622011
Embedded 1-Mb ReRAM-based computing-in-memory macro with multibit input and weight for CNN-based AI edge processors
CX Xue, WH Chen, JS Liu, JF Li, WY Lin, WE Lin, JH Wang, WC Wei, ...
IEEE Journal of Solid-State Circuits 55 (1), 203-215, 2019
602019
A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices
CX Xue, YC Chiu, TW Liu, TY Huang, JS Liu, TW Chang, HY Kao, ...
Nature Electronics 4 (1), 81-90, 2021
502021
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