Azure Accelerated Networking: SmartNICs in the Public Cloud D Firestone, A Putnam, S Mundkur, D Chiou, A Dabagh, M Andrewartha, ... 15th {USENIX} Symposium on Networked Systems Design and Implementation …, 2018 | 796 | 2018 |
Bridging the performance-programmability gap for fpgas via opencl: A case study with opendwarfs K Krommydas, AE Helal, A Verma, WC Feng Computer Science Technical Reports, 2016 | 23 | 2016 |
Accelerating Workloads on FPGAs via OpenCL: A Case Study with OpenDwarfs A Verma, AE Helal, K Krommydas, WC Feng Computer Science Technical Reports, 2016 | 23 | 2016 |
Developing dynamic profiling and debugging support in OpenCL for FPGAs A Verma, H Zhou, S Booth, R King, J Coole, A Keep, J Marshall, W Feng Proceedings of the 54th Annual Design Automation Conference 2017, 1-6, 2017 | 17 | 2017 |
Portable Parallel Design of Weighted Multi-Dimensional Scaling for Real-Time Data Analysis S Dash, A Verma, C North, W Feng High Performance Computing and Communications; IEEE 15th International …, 2017 | 7 | 2017 |
Method to Manufacture Highly Conductive Vias and PROM Memory Cells by Application of Electric Pulses M Orlowski, G Ghosh, A Verma US Patent App. 15/365,445, 2017 | 2 | 2017 |
SYSTEM AND METHOD FOR PROCESSING NETWORKING PACKETS USING A REORDER QUEUE T Tan, A Verma, T Garg, TC Swanson US Patent App. 18/337,403, 2024 | | 2024 |
Cache memory supporting data operations with parametrized latency and throughput A Abdelsalam, VS Gondaliya, A Verma, R Groza Jr, D Lee, E Hamed US Patent App. 18/109,713, 2024 | | 2024 |
On the Programmability and Performance of OpenCL Designs for FPGA A Verma Virginia Tech, 2018 | | 2018 |
Low-k/Cu Resistive 2-Level PROM Memory Collocated with CMOS Back-End Metallization A Verma, G Ghosh, S King, M Orlowski 62nd AVS, 2015 | | 2015 |