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Daesung Kim
Daesung Kim
KAIST, SK hynix
Verified email at kaist.ac.kr
Title
Cited by
Cited by
Year
Block-wise concatenated BCH codes for NAND flash memories
S Cho, D Kim, J Choi, J Ha
IEEE Transactions on Communications 62 (4), 1164-1177, 2014
652014
Electronic device and method of operating the same
DS Kim, SY Kang, JS Kim
US Patent 11,501,170, 2022
202022
Quasi-primitive block-wise concatenated BCH codes with collaborative decoding for NAND flash memories
D Kim, J Ha
IEEE Transactions on Communications 63 (10), 3482-3496, 2015
202015
Symmetric block-wise concatenated BCH codes for NAND flash memories
D Kim, KR Narayanan, J Ha
IEEE Transactions on Communications 66 (10), 4365-4380, 2018
182018
Flash memory system and operating method thereof
JS Ha, D Kim
US Patent 9,619,327, 2017
182017
Quasi-primitive block-wise concatenated BCH codes for NAND flash memories
D Kim, J Ha
2014 IEEE Information Theory Workshop (ITW 2014), 611-615, 2014
142014
Flash memory system and operating method thereof
JS Ha, D Kim, S Jeong
US Patent 9,710,327, 2017
102017
Controller and operating method thereof
SH Yun, SY Kang, DS Kim
US Patent 11,450,400, 2022
92022
Serial quasi-primitive BC-BCH codes for NAND flash memories
D Kim, J Ha
2016 IEEE International Conference on Communications (ICC), 1-6, 2016
92016
Energy-efficient symmetric BC-BCH decoder architecture for mobile storages
S Hwang, S Moon, J Jung, D Kim, IC Park, J Ha, Y Lee
IEEE Transactions on Circuits and Systems I: Regular Papers 66 (11), 4462-4475, 2019
82019
Memory controller, semiconductor memory system and operating method thereof
JS Ha, SH Lee, D Kim
US Patent 10,200,063, 2019
82019
Controller, semiconductor memory system and operating method thereof
JS Ha, D Kim, S Jeong
US Patent 10,521,291, 2019
72019
On the soft information extraction from hard-decision outputs in MLC NAND flash memory
D Kim, J Choi, J Ha
2012 IEEE Global Communications Conference (GLOBECOM), 3208-3213, 2012
72012
An energy-optimized (37840, 34320) symmetric BC-BCH decoder for healthy mobile storages
S Hwang, J Jung, D Kim, J Ha, IC Park, Y Lee
2017 IEEE Asian Solid-State Circuits Conference (A-SSCC), 169-172, 2017
62017
Apparatus and method for controlling a read voltage in a memory system
DS Kim
US Patent 11,526,298, 2022
52022
LDPC decoder, semiconductor memory system, and operating method thereof
D Kim, K Soon-Young, BS Jeong
US Patent 11,005,499, 2021
52021
Controller and operating method thereof
JS Ha, D Kim
US Patent 10,445,175, 2019
52019
Information set analysis of polar codes
D Kim, K Oh, D Kim, J Ha
2016 International Conference on Information and Communication Technology …, 2016
52016
A paired-page reading scheme for NAND flash memory
S Lee, D Kim, J Ha
2016 International Conference on Information and Communication Technology …, 2016
52016
Memory controller
DS Kim
US Patent 11,050,438, 2021
42021
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