| Improved power/EM side-channel attack resistance of 128-bit AES engines with random fast voltage dithering A Singh, M Kar, SK Mathew, A Rajan, V De, S Mukhopadhyay IEEE Journal of Solid-State Circuits 54 (2), 569-583, 2018 | 91 | 2018 |
| RaPiD: AI accelerator for ultra-low precision training and inference S Venkataramani, V Srinivasan, W Wang, S Sen, J Zhang, A Agrawal, ... 2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture …, 2021 | 88 | 2021 |
| 9.1 A 7nm 4-core AI chip with 25.6 TFLOPS hybrid FP8 training, 102.4 TOPS INT4 inference and workload-aware throttling A Agrawal, SK Lee, J Silberman, M Ziegler, M Kang, S Venkataramani, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 144-146, 2021 | 85 | 2021 |
| Reducing power side-channel information leakage of AES engines using fully integrated inductive voltage regulator M Kar, A Singh, SK Mathew, A Rajan, V De, S Mukhopadhyay IEEE Journal of Solid-State Circuits 53 (8), 2399-2414, 2018 | 71 | 2018 |
| 8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulator M Kar, A Singh, S Mathew, A Rajan, V De, S Mukhopadhyay 2017 IEEE International Solid-State Circuits Conference (ISSCC), 142-143, 2017 | 69 | 2017 |
| A 617-TOPS/W all-digital binary neural network accelerator in 10-nm FinFET CMOS PC Knag, GK Chen, HE Sumbul, R Kumar, SK Hsu, A Agarwal, M Kar, ... IEEE journal of solid-state circuits 56 (4), 1082-1092, 2020 | 57 | 2020 |
| Enhanced power and electromagnetic SCA resistance of encryption engines via a security-aware integrated all-digital LDO A Singh, M Kar, VCK Chekuri, SK Mathew, A Rajan, V De, ... IEEE Journal of Solid-State Circuits 55 (2), 478-493, 2019 | 55 | 2019 |
| Energy efficient and side-channel secure cryptographic hardware for IoT-edge nodes A Singh, N Chawla, JH Ko, M Kar, S Mukhopadhyay IEEE Internet of Things Journal 6 (1), 421-434, 2018 | 55 | 2018 |
| 25.3 A 128b AES engine with higher resistance to power and electromagnetic side-channel attacks enabled by a security-aware integrated all-digital low-dropout regulator A Singh, M Kar, S Mathew, A Rajan, V De, S Mukhopadhyay 2019 IEEE International Solid-State Circuits Conference-(ISSCC), 404-406, 2019 | 50 | 2019 |
| An all-digital fully integrated inductive buck regulator with a 250-MHz multi-sampled compensator and a lightweight auto-tuner in 130-nm CMOS M Kar, A Singh, A Rajan, V De, S Mukhopadhyay IEEE Journal of Solid-State Circuits 52 (7), 1825-1835, 2017 | 46 | 2017 |
| Exploring power attack protection of resource constrained encryption engines using integrated low-drop-out regulators A Singh, M Kar, JH Ko, S Mukhopadhyay 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 34 | 2015 |
| Exploiting fully integrated inductive voltage regulators to improve side channel resistance of encryption engines M Kar, A Singh, S Mathew, A Rajan, V De, S Mukhopadhyay Proceedings of the 2016 International Symposium on Low Power Electronics and …, 2016 | 31 | 2016 |
| Multigated carbon nanotube field effect transistors-based physically unclonable functions as security keys N Kumar, J Chen, M Kar, SK Sitaraman, S Mukhopadhyay, S Kumar IEEE Internet of Things Journal 6 (1), 325-334, 2018 | 26 | 2018 |
| Application inference using machine learning based side channel analysis N Chawla, A Singh, M Kar, S Mukhopadhyay 2019 International Joint Conference on Neural Networks (IJCNN), 1-8, 2019 | 24 | 2019 |
| Integrated all-digital low-dropout regulator as a countermeasure to power attack in encryption engines A Singh, M Kar, A Rajan, V De, S Mukhopadhyay 2016 IEEE International Symposium on Hardware Oriented Security and Trust …, 2016 | 24 | 2016 |
| A 7-nm four-core mixed-precision AI chip with 26.2-TFLOPS hybrid-FP8 training, 104.9-TOPS INT4 inference, and workload-aware throttling SK Lee, A Agrawal, J Silberman, M Ziegler, M Kang, S Venkataramani, ... IEEE Journal of Solid-State Circuits 57 (1), 182-197, 2021 | 23 | 2021 |
| A digital low-dropout regulator with autotuned PID compensator and dynamic gain control for improved transient performance under process variations and aging A Singh, M Kar, VCK Chekuri, SK Mathew, A Rajan, V De, ... IEEE Transactions on Power Electronics 35 (3), 3242-3253, 2019 | 22 | 2019 |
| Impact of inductive integrated voltage regulator on the power attack vulnerability of encryption engines: A simulation study M Kar, D Lie, M Wolf, V De, S Mukhopadhyay Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 20 | 2014 |
| A 4900- m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key … R Kumar, V Suresh, M Kar, S Satpathy, MA Anders, H Kaul, A Agarwal, ... IEEE Journal of Solid-State Circuits 55 (4), 945-955, 2020 | 19 | 2020 |
| Exploiting on-chip power management for side-channel security A Singh, M Kar, S Mathew, A Rajan, V De, S Mukhopadhyay 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 401-406, 2018 | 16 | 2018 |
