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Rangharajan Venkatesan
Rangharajan Venkatesan
Senior Research Scientist
Verified email at nvidia.com - Homepage
Title
Cited by
Cited by
Year
SCNN: An accelerator for compressed-sparse convolutional neural networks
A Parashar, M Rhu, A Mukkara, A Puglielli, R Venkatesan, B Khailany, ...
ACM SIGARCH computer architecture news 45 (2), 27-40, 2017
9972017
MACACO: Modeling and analysis of circuits for approximate computing
R Venkatesan, A Agarwal, K Roy, A Raghunathan
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 667-673, 2011
3072011
Timeloop: A systematic approach to dnn accelerator evaluation
A Parashar, P Raina, YS Shao, YH Chen, VA Ying, A Mukkara, ...
2019 IEEE international symposium on performance analysis of systems and …, 2019
1992019
Simba: Scaling deep-learning inference with multi-chip-module-based architecture
YS Shao, J Clemons, R Venkatesan, B Zimmer, M Fojtik, N Jiang, B Keller, ...
Proceedings of the 52nd Annual IEEE/ACM International Symposium on …, 2019
1912019
TapeCache: A high density, energy efficient cache based on domain wall memory
R Venkatesan, V Kozhikkottu, C Augustine, A Raychowdhury, K Roy, ...
Proceedings of the 2012 ACM/IEEE international symposium on Low power …, 2012
1632012
Spin-transfer torque memories: Devices, circuits, and systems
X Fong, Y Kim, R Venkatesan, SH Choday, A Raghunathan, K Roy
Proceedings of the IEEE 104 (7), 1449-1488, 2016
1612016
Dwm-tapestri-an energy efficient all-spin cache using domain wall shift based writes
R Venkatesan, M Sharad, K Roy, A Raghunathan
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2013
1102013
SPINDLE: SPINtronic deep learning engine for large-scale neuromorphic computing
SG Ramasubramanian, R Venkatesan, M Sharad, K Roy, A Raghunathan
2014 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2014
992014
Stag: Spintronic-tape architecture for gpgpu cache hierarchies
R Venkatesan, SG Ramasubramanian, S Venkataramani, K Roy, ...
ACM SIGARCH Computer Architecture News 42 (3), 253-264, 2014
862014
Magnet: A modular accelerator generator for neural networks
R Venkatesan, YS Shao, M Wang, J Clemons, S Dai, M Fojtik, B Keller, ...
2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2019
702019
A modular digital VLSI flow for high-productivity SoC design
B Khailany, R Venkatesan, J Clemons, JS Emer, M Fojtik, A Klinefelter, ...
Proceedings of the 55th Annual Design Automation Conference, 1-6, 2018
502018
A 0.32–128 TOPS, scalable multi-chip-module-based deep neural network inference accelerator with ground-referenced signaling in 16 nm
B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
IEEE Journal of Solid-State Circuits 55 (4), 920-932, 2020
492020
Analog/mixed-signal hardware error modeling for deep learning inference
AS Rekhi, B Zimmer, N Nedovic, N Liu, R Venkatesan, M Wang, ...
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019
482019
Spintastic: Spin-based stochastic logic for energy-efficient computing
R Venkatesan, S Venkataramani, X Fong, K Roy, A Raghunathan
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
442015
Cache design with domain wall memory
R Venkatesan, VJ Kozhikkottu, M Sharad, C Augustine, A Raychowdhury, ...
IEEE Transactions on Computers 65 (4), 1010-1024, 2015
412015
STAxCache: An approximate, energy efficient STT-MRAM cache
A Ranjan, S Venkataramani, Z Pajouhi, R Venkatesan, K Roy, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
402017
A 0.11 pj/op, 0.32-128 tops, scalable multi-chip-module-based deep neural network accelerator with ground-reference signaling in 16nm
B Zimmer, R Venkatesan, YS Shao, J Clemons, M Fojtik, N Jiang, B Keller, ...
2019 Symposium on VLSI Circuits, C300-C301, 2019
392019
A 22nm high performance embedded DRAM SoC technology featuring tri-gate transistors and MIMCAP COB
R Brain, A Baran, N Bisnik, HP Chen, SJ Choi, A Chugh, M Fradkin, ...
2013 Symposium on VLSI Technology, T16-T17, 2013
372013
Multi-level magnetic RAM using domain wall shift for energy-efficient, high-density caches
M Sharad, R Venkatesan, A Raghunathan, K Roy
International Symposium on Low Power Electronics and Design (ISLPED), 64-69, 2013
362013
Buffets: An efficient and composable storage idiom for explicit decoupled data orchestration
M Pellauer, YS Shao, J Clemons, N Crago, K Hegde, R Venkatesan, ...
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
332019
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